Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22542059	15549	0	0
attest_sw_binding_0_rd_A	22542059	2955	0	0
attest_sw_binding_1_rd_A	22542059	2828	0	0
attest_sw_binding_2_rd_A	22542059	2929	0	0
attest_sw_binding_3_rd_A	22542059	3167	0	0
attest_sw_binding_4_rd_A	22542059	2903	0	0
attest_sw_binding_5_rd_A	22542059	3060	0	0
attest_sw_binding_6_rd_A	22542059	3152	0	0
attest_sw_binding_7_rd_A	22542059	3080	0	0
intr_enable_rd_A	22542059	3928	0	0
key_version_rd_A	22542059	2950	0	0
max_creator_key_ver_regwen_rd_A	22542059	2990	0	0
max_owner_int_key_ver_regwen_rd_A	22542059	3137	0	0
max_owner_key_ver_regwen_rd_A	22542059	3175	0	0
reseed_interval_regwen_rd_A	22542059	2918	0	0
salt_0_rd_A	22542059	3096	0	0
salt_1_rd_A	22542059	3216	0	0
salt_2_rd_A	22542059	3086	0	0
salt_3_rd_A	22542059	3141	0	0
salt_4_rd_A	22542059	3046	0	0
salt_5_rd_A	22542059	2910	0	0
salt_6_rd_A	22542059	3077	0	0
salt_7_rd_A	22542059	3119	0	0
sealing_sw_binding_0_rd_A	22542059	3038	0	0
sealing_sw_binding_1_rd_A	22542059	3086	0	0
sealing_sw_binding_2_rd_A	22542059	3196	0	0
sealing_sw_binding_3_rd_A	22542059	3266	0	0
sealing_sw_binding_4_rd_A	22542059	3125	0	0
sealing_sw_binding_5_rd_A	22542059	3133	0	0
sealing_sw_binding_6_rd_A	22542059	3024	0	0
sealing_sw_binding_7_rd_A	22542059	3283	0	0
sideload_clear_rd_A	22542059	3096	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	15549	0	0
T29	28115	471	0	0
T52	12663	0	0	0
T60	10473	0	0	0
T67	38081	428	0	0
T73	0	600	0	0
T93	0	194	0	0
T113	767	0	0	0
T120	0	293	0	0
T137	0	294	0	0
T138	0	108	0	0
T139	0	21	0	0
T140	0	397	0	0
T148	140616	0	0	0
T149	3185	0	0	0
T150	3345	0	0	0
T151	8033	0	0	0
T152	8958	0	0	0
T153	0	302	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2955	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	67	0	0
T121	4739	0	0	0
T139	0	30	0	0
T140	0	50	0	0
T146	7837	0	0	0
T167	0	23	0	0
T174	0	17	0	0
T193	0	81	0	0
T194	0	7	0	0
T195	0	12	0	0
T196	0	45	0	0
T197	0	15	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2828	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	45	0	0
T121	4739	0	0	0
T139	0	24	0	0
T140	0	22	0	0
T146	7837	0	0	0
T167	0	30	0	0
T174	0	10	0	0
T193	0	88	0	0
T194	0	12	0	0
T195	0	16	0	0
T196	0	42	0	0
T197	0	4	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2929	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	49	0	0
T121	4739	0	0	0
T139	0	29	0	0
T140	0	42	0	0
T146	7837	0	0	0
T167	0	8	0	0
T174	0	8	0	0
T193	0	73	0	0
T194	0	22	0	0
T195	0	7	0	0
T196	0	52	0	0
T197	0	14	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3167	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	76	0	0
T121	4739	0	0	0
T139	0	20	0	0
T140	0	40	0	0
T146	7837	0	0	0
T167	0	10	0	0
T174	0	30	0	0
T193	0	80	0	0
T194	0	14	0	0
T195	0	13	0	0
T196	0	46	0	0
T197	0	11	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2903	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	53	0	0
T121	4739	0	0	0
T139	0	39	0	0
T140	0	16	0	0
T146	7837	0	0	0
T167	0	18	0	0
T174	0	12	0	0
T193	0	57	0	0
T194	0	10	0	0
T195	0	6	0	0
T196	0	48	0	0
T197	0	9	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3060	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	81	0	0
T121	4739	0	0	0
T139	0	16	0	0
T140	0	33	0	0
T146	7837	0	0	0
T167	0	20	0	0
T174	0	27	0	0
T193	0	70	0	0
T194	0	22	0	0
T195	0	15	0	0
T196	0	42	0	0
T197	0	24	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3152	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	42	0	0
T121	4739	0	0	0
T139	0	37	0	0
T140	0	24	0	0
T146	7837	0	0	0
T174	0	29	0	0
T193	0	74	0	0
T194	0	16	0	0
T195	0	29	0	0
T196	0	30	0	0
T197	0	25	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0
T203	0	3	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3080	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	81	0	0
T121	4739	0	0	0
T139	0	23	0	0
T140	0	40	0	0
T146	7837	0	0	0
T167	0	29	0	0
T174	0	17	0	0
T193	0	93	0	0
T194	0	20	0	0
T195	0	7	0	0
T196	0	39	0	0
T197	0	10	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3928	0	0
T6	114159	67	0	0
T30	4743	0	0	0
T48	10765	0	0	0
T64	0	52	0	0
T120	0	84	0	0
T139	0	51	0	0
T140	0	54	0	0
T165	23025	0	0	0
T193	0	122	0	0
T204	0	96	0	0
T205	0	61	0	0
T206	0	4	0	0
T207	0	19	0	0
T208	5931	0	0	0
T209	1095	0	0	0
T210	1232	0	0	0
T211	1317	0	0	0
T212	21033	0	0	0
T213	7062	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2950	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	60	0	0
T121	4739	0	0	0
T139	0	28	0	0
T140	0	28	0	0
T146	7837	0	0	0
T167	0	16	0	0
T174	0	17	0	0
T193	0	34	0	0
T194	0	14	0	0
T195	0	15	0	0
T196	0	37	0	0
T197	0	11	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2990	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	51	0	0
T121	4739	0	0	0
T139	0	14	0	0
T140	0	15	0	0
T146	7837	0	0	0
T167	0	8	0	0
T174	0	26	0	0
T193	0	60	0	0
T194	0	29	0	0
T195	0	26	0	0
T196	0	53	0	0
T197	0	28	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3137	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	56	0	0
T121	4739	0	0	0
T139	0	16	0	0
T140	0	24	0	0
T146	7837	0	0	0
T167	0	22	0	0
T174	0	14	0	0
T193	0	54	0	0
T194	0	15	0	0
T195	0	4	0	0
T196	0	35	0	0
T197	0	29	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3175	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	93	0	0
T121	4739	0	0	0
T139	0	24	0	0
T140	0	47	0	0
T146	7837	0	0	0
T167	0	14	0	0
T174	0	17	0	0
T193	0	68	0	0
T194	0	24	0	0
T195	0	2	0	0
T196	0	38	0	0
T197	0	18	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2918	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	33	0	0
T121	4739	0	0	0
T139	0	16	0	0
T140	0	25	0	0
T146	7837	0	0	0
T167	0	28	0	0
T174	0	27	0	0
T193	0	42	0	0
T194	0	8	0	0
T195	0	19	0	0
T196	0	41	0	0
T197	0	9	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3096	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	69	0	0
T121	4739	0	0	0
T139	0	27	0	0
T140	0	45	0	0
T146	7837	0	0	0
T167	0	9	0	0
T174	0	12	0	0
T193	0	36	0	0
T194	0	11	0	0
T195	0	4	0	0
T196	0	38	0	0
T197	0	21	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3216	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	67	0	0
T121	4739	0	0	0
T139	0	29	0	0
T140	0	40	0	0
T146	7837	0	0	0
T167	0	23	0	0
T174	0	8	0	0
T193	0	58	0	0
T194	0	11	0	0
T195	0	21	0	0
T196	0	50	0	0
T197	0	17	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3086	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	43	0	0
T121	4739	0	0	0
T139	0	27	0	0
T140	0	35	0	0
T146	7837	0	0	0
T167	0	16	0	0
T174	0	13	0	0
T193	0	88	0	0
T194	0	17	0	0
T195	0	18	0	0
T196	0	51	0	0
T197	0	10	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3141	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	63	0	0
T121	4739	0	0	0
T139	0	40	0	0
T140	0	39	0	0
T146	7837	0	0	0
T167	0	24	0	0
T174	0	15	0	0
T193	0	63	0	0
T194	0	16	0	0
T195	0	15	0	0
T196	0	30	0	0
T197	0	29	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3046	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	54	0	0
T121	4739	0	0	0
T139	0	20	0	0
T140	0	17	0	0
T146	7837	0	0	0
T167	0	13	0	0
T174	0	22	0	0
T193	0	62	0	0
T194	0	17	0	0
T196	0	33	0	0
T197	0	17	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0
T214	0	8	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	2910	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	56	0	0
T121	4739	0	0	0
T139	0	32	0	0
T140	0	17	0	0
T146	7837	0	0	0
T167	0	15	0	0
T174	0	26	0	0
T193	0	47	0	0
T194	0	24	0	0
T195	0	22	0	0
T196	0	66	0	0
T197	0	16	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3077	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	62	0	0
T121	4739	0	0	0
T139	0	46	0	0
T140	0	26	0	0
T146	7837	0	0	0
T167	0	21	0	0
T174	0	5	0	0
T193	0	62	0	0
T194	0	10	0	0
T195	0	16	0	0
T196	0	56	0	0
T197	0	6	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3119	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	65	0	0
T121	4739	0	0	0
T139	0	15	0	0
T140	0	31	0	0
T146	7837	0	0	0
T167	0	21	0	0
T174	0	15	0	0
T193	0	56	0	0
T194	0	15	0	0
T195	0	17	0	0
T196	0	36	0	0
T197	0	12	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3038	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	38	0	0
T121	4739	0	0	0
T139	0	28	0	0
T140	0	34	0	0
T146	7837	0	0	0
T167	0	27	0	0
T174	0	22	0	0
T193	0	60	0	0
T194	0	23	0	0
T195	0	7	0	0
T196	0	62	0	0
T197	0	20	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3086	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	67	0	0
T121	4739	0	0	0
T139	0	42	0	0
T140	0	15	0	0
T146	7837	0	0	0
T167	0	28	0	0
T174	0	23	0	0
T193	0	60	0	0
T194	0	19	0	0
T195	0	11	0	0
T196	0	57	0	0
T197	0	5	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3196	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	69	0	0
T121	4739	0	0	0
T139	0	27	0	0
T140	0	41	0	0
T146	7837	0	0	0
T167	0	15	0	0
T174	0	15	0	0
T193	0	85	0	0
T194	0	18	0	0
T195	0	19	0	0
T196	0	79	0	0
T197	0	12	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3266	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	67	0	0
T121	4739	0	0	0
T139	0	43	0	0
T140	0	36	0	0
T146	7837	0	0	0
T167	0	28	0	0
T174	0	15	0	0
T193	0	53	0	0
T194	0	19	0	0
T195	0	11	0	0
T196	0	70	0	0
T197	0	18	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3125	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	38	0	0
T121	4739	0	0	0
T139	0	40	0	0
T140	0	32	0	0
T146	7837	0	0	0
T167	0	37	0	0
T174	0	16	0	0
T193	0	72	0	0
T194	0	7	0	0
T195	0	14	0	0
T196	0	52	0	0
T197	0	24	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3133	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	98	0	0
T121	4739	0	0	0
T139	0	33	0	0
T140	0	31	0	0
T146	7837	0	0	0
T167	0	30	0	0
T174	0	14	0	0
T193	0	64	0	0
T194	0	16	0	0
T195	0	6	0	0
T196	0	41	0	0
T197	0	12	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3024	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	33	0	0
T121	4739	0	0	0
T139	0	21	0	0
T140	0	19	0	0
T146	7837	0	0	0
T167	0	14	0	0
T174	0	24	0	0
T193	0	67	0	0
T194	0	20	0	0
T195	0	6	0	0
T196	0	74	0	0
T197	0	33	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3283	0	0
T25	9717	0	0	0
T26	2647	0	0	0
T120	58392	60	0	0
T121	4739	0	0	0
T139	0	53	0	0
T140	0	24	0	0
T146	7837	0	0	0
T167	0	42	0	0
T174	0	16	0	0
T193	0	56	0	0
T194	0	5	0	0
T195	0	7	0	0
T196	0	60	0	0
T197	0	11	0	0
T198	12124	0	0	0
T199	6635	0	0	0
T200	13139	0	0	0
T201	28561	0	0	0
T202	4681	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22542059	3096	0	0
T7	11427	0	0	0
T34	9827	0	0	0
T35	7198	0	0	0
T120	0	49	0	0
T139	0	14	0	0
T140	0	47	0	0
T174	0	16	0	0
T193	0	41	0	0
T194	0	13	0	0
T195	0	15	0	0
T196	0	41	0	0
T197	0	17	0	0
T215	9549	4	0	0
T216	8867	0	0	0
T217	9286	0	0	0
T218	4602	0	0	0
T219	9144	0	0	0
T220	11286	0	0	0
T221	6615	0	0	0