Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3536373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

632862

1

T1

530

T2

231

T3

343

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3739372	1			T1	550		T2	4046		T3	804
values[0x0]	213614	1			T1	207		T2	54		T3	140
values[0x1]	216249	1			T1	219		T2	60		T3	137

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2419066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1750169

1

T1

641

T2

1542

T3

554

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13159	1			T1	1		T2	14		T3	8
valid_sources[0x01]	13552	1			T1	2		T2	12		T3	7
valid_sources[0x02]	18306	1			T1	3		T2	13		T3	3
valid_sources[0x03]	14107	1			T1	5		T2	18		T3	1
valid_sources[0x04]	14197	1			T1	3		T2	14		T5	2
valid_sources[0x05]	18908	1			T1	5		T2	16		T3	6
valid_sources[0x06]	14190	1			T2	15		T3	8		T5	4
valid_sources[0x07]	23205	1			T1	4		T2	13		T3	12
valid_sources[0x08]	13504	1			T1	3		T2	20		T3	7
valid_sources[0x09]	16335	1			T1	5		T2	34		T3	9
valid_sources[0x0a]	15161	1			T1	4		T2	15		T3	7
valid_sources[0x0b]	14398	1			T1	6		T2	14		T5	3
valid_sources[0x0c]	14960	1			T1	5		T2	23		T5	4
valid_sources[0x0d]	15282	1			T1	4		T2	19		T3	6
valid_sources[0x0e]	13340	1			T1	2		T2	13		T3	22
valid_sources[0x0f]	14544	1			T1	5		T2	14		T5	2
valid_sources[0x10]	13737	1			T1	7		T2	22		T5	2
valid_sources[0x11]	13437	1			T1	2		T2	18		T5	3
valid_sources[0x12]	15913	1			T1	2		T2	17		T3	5
valid_sources[0x13]	23521	1			T1	5		T2	11		T3	16
valid_sources[0x14]	13749	1			T1	3		T2	20		T3	2
valid_sources[0x15]	18188	1			T1	9		T2	13		T3	8
valid_sources[0x16]	20504	1			T1	3		T2	11		T3	1
valid_sources[0x17]	46213	1			T1	1		T2	13		T3	7
valid_sources[0x18]	20809	1			T1	3		T2	24		T3	10
valid_sources[0x19]	14202	1			T1	3		T2	10		T3	4
valid_sources[0x1a]	18375	1			T1	4		T2	13		T3	11
valid_sources[0x1b]	13489	1			T1	4		T2	19		T3	3
valid_sources[0x1c]	13696	1			T1	3		T2	14		T5	3
valid_sources[0x1d]	14798	1			T1	4		T2	19		T5	2
valid_sources[0x1e]	15666	1			T1	4		T2	16		T4	4
valid_sources[0x1f]	16862	1			T1	2		T2	12		T3	1
valid_sources[0x20]	13743	1			T1	5		T2	21		T3	3
valid_sources[0x21]	17502	1			T1	3		T2	28		T5	4
valid_sources[0x22]	17403	1			T1	3		T2	11		T3	15
valid_sources[0x23]	15252	1			T1	5		T2	13		T3	10
valid_sources[0x24]	15373	1			T1	1		T2	12		T5	5
valid_sources[0x25]	14513	1			T1	7		T2	18		T5	5
valid_sources[0x26]	16159	1			T1	4		T2	10		T3	2
valid_sources[0x27]	21200	1			T1	3		T2	27		T3	1
valid_sources[0x28]	19220	1			T1	4		T2	12		T3	3
valid_sources[0x29]	16844	1			T1	1		T2	18		T3	6
valid_sources[0x2a]	16070	1			T1	3		T2	12		T3	1
valid_sources[0x2b]	19226	1			T1	1		T2	15		T3	1
valid_sources[0x2c]	19673	1			T1	9		T2	11		T3	10
valid_sources[0x2d]	13629	1			T1	3		T2	8		T5	2
valid_sources[0x2e]	14073	1			T1	3		T2	16		T4	122
valid_sources[0x2f]	15393	1			T1	4		T2	24		T3	5
valid_sources[0x30]	16447	1			T1	1		T2	13		T3	4
valid_sources[0x31]	13270	1			T1	2		T2	18		T3	8
valid_sources[0x32]	15412	1			T1	3		T2	20		T3	5
valid_sources[0x33]	14972	1			T1	7		T2	11		T5	2
valid_sources[0x34]	16240	1			T1	2		T2	13		T3	3
valid_sources[0x35]	14997	1			T1	2		T2	16		T3	1
valid_sources[0x36]	15448	1			T1	3		T2	12		T3	15
valid_sources[0x37]	14133	1			T2	16		T5	3		T4	4
valid_sources[0x38]	13797	1			T1	4		T2	20		T3	9
valid_sources[0x39]	14372	1			T1	5		T2	7		T3	19
valid_sources[0x3a]	14478	1			T1	1		T2	14		T3	1
valid_sources[0x3b]	16780	1			T1	4		T2	19		T3	12
valid_sources[0x3c]	17877	1			T1	3		T2	24		T3	3
valid_sources[0x3d]	31416	1			T1	1		T2	16		T3	1
valid_sources[0x3e]	15920	1			T1	2		T2	14		T3	11
valid_sources[0x3f]	14144	1			T1	2		T2	15		T3	3
valid_sources[0x40]	13945	1			T1	1		T2	14		T3	4
valid_sources[0x41]	14330	1			T1	1		T2	14		T3	6
valid_sources[0x42]	14448	1			T1	3		T2	22		T3	2
valid_sources[0x43]	13973	1			T1	7		T2	12		T3	20
valid_sources[0x44]	24448	1			T1	2		T2	18		T3	6
valid_sources[0x45]	13382	1			T1	4		T2	10		T3	7
valid_sources[0x46]	24289	1			T1	4		T2	20		T3	2
valid_sources[0x47]	14910	1			T1	2		T2	21		T3	2
valid_sources[0x48]	13578	1			T1	4		T2	10		T4	7
valid_sources[0x49]	13134	1			T1	2		T2	18		T3	15
valid_sources[0x4a]	16244	1			T1	3		T2	12		T3	14
valid_sources[0x4b]	32136	1			T1	3		T2	12		T3	6
valid_sources[0x4c]	15795	1			T1	3		T2	9		T3	2
valid_sources[0x4d]	13007	1			T1	3		T2	14		T3	11
valid_sources[0x4e]	17281	1			T1	3		T2	17		T3	8
valid_sources[0x4f]	16497	1			T1	5		T2	21		T3	7
valid_sources[0x50]	13802	1			T1	3		T2	19		T5	2
valid_sources[0x51]	13548	1			T1	5		T2	22		T3	2
valid_sources[0x52]	12777	1			T1	7		T2	26		T5	3
valid_sources[0x53]	15215	1			T1	3		T2	8		T5	4
valid_sources[0x54]	12754	1			T1	3		T2	21		T5	3
valid_sources[0x55]	13023	1			T1	3		T2	22		T3	4
valid_sources[0x56]	14148	1			T1	2		T2	22		T3	1
valid_sources[0x57]	14408	1			T1	3		T2	12		T3	8
valid_sources[0x58]	32866	1			T1	7		T2	17		T5	2
valid_sources[0x59]	20512	1			T1	3		T2	17		T3	7
valid_sources[0x5a]	17159	1			T1	7		T2	15		T15	9
valid_sources[0x5b]	13710	1			T1	3		T2	13		T3	1
valid_sources[0x5c]	14845	1			T1	6		T2	14		T3	11
valid_sources[0x5d]	14014	1			T1	5		T2	18		T3	7
valid_sources[0x5e]	14515	1			T1	8		T2	12		T3	7
valid_sources[0x5f]	14074	1			T1	3		T2	22		T5	3
valid_sources[0x60]	13848	1			T1	5		T2	10		T3	1
valid_sources[0x61]	13828	1			T1	6		T2	11		T5	2
valid_sources[0x62]	20824	1			T1	5		T2	12		T5	6
valid_sources[0x63]	14598	1			T1	3		T2	27		T3	18
valid_sources[0x64]	16402	1			T1	8		T2	13		T3	4
valid_sources[0x65]	16073	1			T1	2		T2	16		T5	1
valid_sources[0x66]	13144	1			T1	3		T2	19		T3	4
valid_sources[0x67]	13647	1			T1	6		T2	11		T3	3
valid_sources[0x68]	17898	1			T1	7		T2	19		T5	3
valid_sources[0x69]	24224	1			T1	1		T2	12		T3	14
valid_sources[0x6a]	13532	1			T1	5		T2	16		T3	1
valid_sources[0x6b]	13091	1			T1	8		T2	18		T3	1
valid_sources[0x6c]	16139	1			T1	5		T2	18		T5	3
valid_sources[0x6d]	14861	1			T1	4		T2	23		T5	3
valid_sources[0x6e]	15909	1			T1	4		T2	16		T3	2
valid_sources[0x6f]	17215	1			T1	2		T2	25		T3	4
valid_sources[0x70]	19791	1			T1	3		T2	13		T3	10
valid_sources[0x71]	15366	1			T1	4		T2	23		T14	1
valid_sources[0x72]	12355	1			T1	5		T2	11		T3	1
valid_sources[0x73]	13130	1			T1	8		T2	8		T3	1
valid_sources[0x74]	13704	1			T1	3		T2	17		T5	2
valid_sources[0x75]	17751	1			T1	4		T2	15		T3	1
valid_sources[0x76]	13397	1			T1	4		T2	21		T3	2
valid_sources[0x77]	13233	1			T1	7		T2	15		T3	7
valid_sources[0x78]	14510	1			T1	3		T2	19		T3	10
valid_sources[0x79]	13515	1			T1	6		T2	20		T5	2
valid_sources[0x7a]	14946	1			T1	6		T2	13		T3	2
valid_sources[0x7b]	13180	1			T1	1		T2	14		T5	2
valid_sources[0x7c]	14781	1			T1	5		T2	14		T5	5
valid_sources[0x7d]	25174	1			T1	3		T2	10		T5	1
valid_sources[0x7e]	14442	1			T1	6		T2	13		T3	2
valid_sources[0x7f]	17742	1			T1	3		T2	13		T3	6
valid_sources[0x80]	13053	1			T1	2		T2	16		T5	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

341574

1

T1

208

T2

174

T3

150

values[0x0]

all_enables

biggest_size

153349

1

T1

160

T2

35

T3

103

values[0x1]

all_enables

biggest_size

137939

1

T1

162

T2

22

T3

90