Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26090800	13397	0	0
attest_sw_binding_0_rd_A	26090800	3617	0	0
attest_sw_binding_1_rd_A	26090800	3670	0	0
attest_sw_binding_2_rd_A	26090800	3433	0	0
attest_sw_binding_3_rd_A	26090800	3571	0	0
attest_sw_binding_4_rd_A	26090800	3557	0	0
attest_sw_binding_5_rd_A	26090800	3679	0	0
attest_sw_binding_6_rd_A	26090800	3391	0	0
attest_sw_binding_7_rd_A	26090800	3362	0	0
intr_enable_rd_A	26090800	4257	0	0
key_version_rd_A	26090800	3431	0	0
max_creator_key_ver_regwen_rd_A	26090800	3641	0	0
max_owner_int_key_ver_regwen_rd_A	26090800	3583	0	0
max_owner_key_ver_regwen_rd_A	26090800	3746	0	0
reseed_interval_regwen_rd_A	26090800	3570	0	0
salt_0_rd_A	26090800	3450	0	0
salt_1_rd_A	26090800	3735	0	0
salt_2_rd_A	26090800	3455	0	0
salt_3_rd_A	26090800	3688	0	0
salt_4_rd_A	26090800	3584	0	0
salt_5_rd_A	26090800	3381	0	0
salt_6_rd_A	26090800	3514	0	0
salt_7_rd_A	26090800	3456	0	0
sealing_sw_binding_0_rd_A	26090800	3583	0	0
sealing_sw_binding_1_rd_A	26090800	3648	0	0
sealing_sw_binding_2_rd_A	26090800	3629	0	0
sealing_sw_binding_3_rd_A	26090800	3716	0	0
sealing_sw_binding_4_rd_A	26090800	3707	0	0
sealing_sw_binding_5_rd_A	26090800	3542	0	0
sealing_sw_binding_6_rd_A	26090800	3650	0	0
sealing_sw_binding_7_rd_A	26090800	3567	0	0
sideload_clear_rd_A	26090800	3470	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	13397	0	0
T20	16001	0	0	0
T24	11983	0	0	0
T42	9623	0	0	0
T53	0	1	0	0
T55	4782	0	0	0
T100	4788	0	0	0
T101	34220	139	0	0
T116	0	729	0	0
T117	0	368	0	0
T127	0	260	0	0
T128	0	152	0	0
T129	0	94	0	0
T130	0	363	0	0
T131	0	166	0	0
T132	0	54	0	0
T134	2622	0	0	0
T135	2282	0	0	0
T136	11531	0	0	0
T137	6769	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3617	0	0
T125	0	4	0	0
T128	35894	31	0	0
T129	16595	0	0	0
T131	0	41	0	0
T160	0	8	0	0
T186	0	54	0	0
T187	0	31	0	0
T188	0	1	0	0
T189	0	26	0	0
T190	0	24	0	0
T191	0	60	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3670	0	0
T121	0	49	0	0
T125	0	13	0	0
T128	35894	19	0	0
T129	16595	0	0	0
T131	0	72	0	0
T186	0	44	0	0
T187	0	30	0	0
T189	0	23	0	0
T190	0	36	0	0
T191	0	39	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	8	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3433	0	0
T121	0	36	0	0
T125	0	23	0	0
T128	35894	27	0	0
T129	16595	0	0	0
T131	0	67	0	0
T186	0	53	0	0
T187	0	44	0	0
T189	0	14	0	0
T190	0	36	0	0
T191	0	57	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T201	0	7	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3571	0	0
T121	0	36	0	0
T125	0	6	0	0
T128	35894	19	0	0
T129	16595	0	0	0
T131	0	60	0	0
T186	0	55	0	0
T187	0	31	0	0
T189	0	20	0	0
T190	0	9	0	0
T191	0	66	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	14	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3557	0	0
T53	4650	0	0	0
T56	14972	5	0	0
T57	11724	0	0	0
T65	14688	0	0	0
T75	84561	0	0	0
T76	27786	0	0	0
T77	4431	0	0	0
T78	8702	0	0	0
T79	3392	0	0	0
T80	949	0	0	0
T125	0	8	0	0
T128	0	2	0	0
T131	0	42	0	0
T160	0	6	0	0
T186	0	48	0	0
T187	0	21	0	0
T189	0	10	0	0
T190	0	22	0	0
T191	0	63	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3679	0	0
T118	2791	1	0	0
T125	0	28	0	0
T128	0	13	0	0
T131	0	67	0	0
T160	0	4	0	0
T186	0	60	0	0
T187	0	47	0	0
T189	0	19	0	0
T190	0	22	0	0
T191	0	71	0	0
T202	11339	0	0	0
T203	6969	0	0	0
T204	3167	0	0	0
T205	6402	0	0	0
T206	50917	0	0	0
T207	6215	0	0	0
T208	4587	0	0	0
T209	7006	0	0	0
T210	8527	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3391	0	0
T121	0	54	0	0
T125	0	17	0	0
T128	35894	21	0	0
T129	16595	0	0	0
T131	0	62	0	0
T186	0	42	0	0
T187	0	31	0	0
T189	0	18	0	0
T190	0	14	0	0
T191	0	49	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	9	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3362	0	0
T121	0	43	0	0
T125	0	11	0	0
T128	35894	9	0	0
T129	16595	0	0	0
T131	0	34	0	0
T160	0	8	0	0
T186	0	46	0	0
T187	0	27	0	0
T189	0	24	0	0
T190	0	24	0	0
T191	0	86	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	4257	0	0
T6	140339	23	0	0
T7	0	50	0	0
T47	114421	44	0	0
T48	96118	0	0	0
T70	0	23	0	0
T123	4825	0	0	0
T128	0	10	0	0
T131	0	78	0	0
T186	0	113	0	0
T187	0	30	0	0
T211	0	5	0	0
T212	0	23	0	0
T213	107972	0	0	0
T214	185075	0	0	0
T215	4945	0	0	0
T216	7373	0	0	0
T217	15194	0	0	0
T218	2075	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3431	0	0
T121	0	58	0	0
T125	0	4	0	0
T128	35894	18	0	0
T129	16595	0	0	0
T131	0	63	0	0
T160	0	2	0	0
T186	0	59	0	0
T187	0	37	0	0
T189	0	33	0	0
T190	0	25	0	0
T191	0	33	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3641	0	0
T121	0	61	0	0
T125	0	12	0	0
T128	35894	12	0	0
T129	16595	0	0	0
T131	0	53	0	0
T160	0	1	0	0
T186	0	67	0	0
T187	0	36	0	0
T189	0	36	0	0
T190	0	20	0	0
T191	0	53	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3583	0	0
T121	0	57	0	0
T125	0	11	0	0
T128	35894	11	0	0
T129	16595	0	0	0
T131	0	67	0	0
T186	0	64	0	0
T187	0	20	0	0
T189	0	17	0	0
T190	0	43	0	0
T191	0	33	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	4	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3746	0	0
T121	0	31	0	0
T125	0	9	0	0
T128	35894	18	0	0
T129	16595	0	0	0
T131	0	67	0	0
T186	0	51	0	0
T187	0	37	0	0
T189	0	45	0	0
T190	0	31	0	0
T191	0	69	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	16	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3570	0	0
T121	0	73	0	0
T125	0	17	0	0
T128	35894	1	0	0
T129	16595	0	0	0
T131	0	49	0	0
T160	0	6	0	0
T186	0	62	0	0
T187	0	30	0	0
T189	0	29	0	0
T190	0	35	0	0
T191	0	69	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3450	0	0
T121	0	67	0	0
T125	0	28	0	0
T128	35894	17	0	0
T129	16595	0	0	0
T131	0	54	0	0
T147	0	6	0	0
T186	0	81	0	0
T187	0	40	0	0
T189	0	24	0	0
T190	0	26	0	0
T191	0	39	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3735	0	0
T121	0	82	0	0
T125	0	6	0	0
T128	35894	28	0	0
T129	16595	0	0	0
T131	0	75	0	0
T160	0	9	0	0
T186	0	60	0	0
T187	0	50	0	0
T189	0	25	0	0
T190	0	26	0	0
T191	0	88	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3455	0	0
T121	0	44	0	0
T125	0	4	0	0
T128	35894	17	0	0
T129	16595	0	0	0
T131	0	58	0	0
T186	0	94	0	0
T187	0	25	0	0
T189	0	20	0	0
T190	0	26	0	0
T191	0	56	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3688	0	0
T121	0	62	0	0
T125	0	17	0	0
T128	35894	4	0	0
T129	16595	0	0	0
T131	0	43	0	0
T160	0	2	0	0
T186	0	47	0	0
T187	0	39	0	0
T189	0	35	0	0
T190	0	35	0	0
T191	0	72	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3584	0	0
T121	0	39	0	0
T125	0	10	0	0
T128	35894	10	0	0
T129	16595	0	0	0
T131	0	75	0	0
T160	0	7	0	0
T186	0	39	0	0
T187	0	15	0	0
T189	0	29	0	0
T190	0	6	0	0
T191	0	39	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3381	0	0
T121	0	63	0	0
T125	0	8	0	0
T128	35894	9	0	0
T129	16595	0	0	0
T131	0	48	0	0
T186	0	76	0	0
T187	0	39	0	0
T189	0	13	0	0
T190	0	6	0	0
T191	0	47	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	15	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3514	0	0
T121	0	32	0	0
T125	0	16	0	0
T128	35894	16	0	0
T129	16595	0	0	0
T131	0	74	0	0
T186	0	52	0	0
T187	0	36	0	0
T189	0	34	0	0
T190	0	30	0	0
T191	0	53	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	8	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3456	0	0
T121	0	52	0	0
T125	0	16	0	0
T128	35894	3	0	0
T129	16595	0	0	0
T131	0	68	0	0
T186	0	65	0	0
T187	0	32	0	0
T189	0	7	0	0
T190	0	35	0	0
T191	0	64	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	24	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3583	0	0
T121	0	50	0	0
T125	0	24	0	0
T128	35894	21	0	0
T129	16595	0	0	0
T131	0	37	0	0
T186	0	51	0	0
T187	0	45	0	0
T189	0	39	0	0
T190	0	22	0	0
T191	0	36	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	13	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3648	0	0
T121	0	65	0	0
T125	0	16	0	0
T128	35894	17	0	0
T129	16595	0	0	0
T131	0	70	0	0
T186	0	53	0	0
T187	0	22	0	0
T189	0	21	0	0
T190	0	23	0	0
T191	0	43	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	19	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3629	0	0
T125	0	20	0	0
T128	35894	30	0	0
T129	16595	0	0	0
T131	0	56	0	0
T160	0	9	0	0
T186	0	66	0	0
T187	0	24	0	0
T189	0	17	0	0
T190	0	26	0	0
T191	0	53	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T219	0	3	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3716	0	0
T121	0	70	0	0
T125	0	12	0	0
T131	40377	61	0	0
T132	20414	0	0	0
T133	59125	0	0	0
T160	0	2	0	0
T166	23409	0	0	0
T186	0	50	0	0
T187	0	17	0	0
T189	0	27	0	0
T190	0	37	0	0
T191	0	68	0	0
T200	0	10	0	0
T220	6103	0	0	0
T221	8995	0	0	0
T222	9807	0	0	0
T223	1604	0	0	0
T224	11872	0	0	0
T225	31133	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3707	0	0
T121	0	67	0	0
T125	0	13	0	0
T131	40377	46	0	0
T132	20414	0	0	0
T133	59125	0	0	0
T160	0	5	0	0
T166	23409	0	0	0
T186	0	49	0	0
T187	0	12	0	0
T189	0	19	0	0
T190	0	15	0	0
T191	0	71	0	0
T200	0	37	0	0
T220	6103	0	0	0
T221	8995	0	0	0
T222	9807	0	0	0
T223	1604	0	0	0
T224	11872	0	0	0
T225	31133	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3542	0	0
T121	0	47	0	0
T125	0	7	0	0
T128	35894	18	0	0
T129	16595	0	0	0
T131	0	63	0	0
T186	0	55	0	0
T187	0	30	0	0
T189	0	23	0	0
T190	0	27	0	0
T191	0	43	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	4	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3650	0	0
T121	0	63	0	0
T125	0	32	0	0
T128	35894	15	0	0
T129	16595	0	0	0
T131	0	52	0	0
T186	0	80	0	0
T187	0	31	0	0
T189	0	24	0	0
T190	0	15	0	0
T191	0	68	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T201	0	2	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3567	0	0
T121	0	34	0	0
T125	0	8	0	0
T128	35894	14	0	0
T129	16595	0	0	0
T131	0	59	0	0
T186	0	76	0	0
T187	0	21	0	0
T189	0	26	0	0
T190	0	20	0	0
T191	0	49	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0
T200	0	12	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26090800	3470	0	0
T121	0	48	0	0
T125	0	13	0	0
T128	35894	28	0	0
T129	16595	0	0	0
T131	0	44	0	0
T160	0	5	0	0
T186	0	63	0	0
T187	0	20	0	0
T189	0	27	0	0
T190	0	22	0	0
T191	0	51	0	0
T192	2621	0	0	0
T193	15969	0	0	0
T194	776	0	0	0
T195	1311	0	0	0
T196	8360	0	0	0
T197	6871	0	0	0
T198	28310	0	0	0
T199	14828	0	0	0