Unified Coverage Report :: Module :: keymgr_ctrl

Module : keymgr_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.80	100.00	98.11		100.00	100.00	90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl	97.80	100.00	98.11		100.00	100.00	90.91

---

Module Instance : tb.dut.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.80	100.00	98.11		100.00	100.00	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.04	99.71	95.29	94.46	100.00	98.65	94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	93.15			93.15
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	95.89			95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	95.89			95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	95.89			95.89
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	97.26			97.26
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	95.89			95.89
u_cnt	100.00			100.00
u_data_en	84.15	97.44	33.33		100.00	90.00	100.00
u_err	94.81	100.00	84.44			100.00
u_hw_sel	100.00	100.00				100.00	100.00
u_key_valid_sync	100.00	100.00				100.00
u_op_state	100.00	100.00	100.00		100.00	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_ctrl

	Line No.	Total	Covered	Percent
TOTAL		194	194	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
ALWAYS	248	3	3	100.00
CONT_ASSIGN	255	1	1	100.00
ALWAYS	261	3	3	100.00
ALWAYS	264	3	3	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
ALWAYS	290	7	7	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	349	21	21	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
ALWAYS	455	79	79	100.00
ALWAYS	681	4	4	100.00
ALWAYS	689	12	12	100.00
ALWAYS	725	5	5	100.00
CONT_ASSIGN	763	1	1	100.00
CONT_ASSIGN	769	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
ALWAYS	808	3	3	100.00
CONT_ASSIGN	818	1	1	100.00
ROUTINE	865	1	1	100.00
ALWAYS	907	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
150	1	1
151	1	1
152	1	1
153	1	1
155	1	1
165	1	1
166	1	1
169	1	1
185	1	1
186	1	1
187	1	1
188	1	1
202	1	1
207	1	1
213	1	1
215	1	1
230	1	1
243	1	1
248	1	1
249	1	1
251	1	1
255	1	1
261	3	3
264	1	1
265	1	1
267	1	1
275	1	1
277	1	1
281	2	2
288	1	1
290	1	1
291	1	1
292	1	1
294	1	1
295	1	1
296	1	1
297	1	1
316	16	16
323	1	1
346	1	1
349	1	1
350	1	1
351	1	1
355	1	1
357	1	1
358	1	1
361	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
373		unreachable
375		unreachable
380	1	1
381	1	1
382	1	1
388	1	1
389	1	1
393	1	1
394	1	1
395	1	1
396	1	1
433	1	1
444	1	1
445	1	1
451	1	1
455	1	1
458	1	1
459	1	1
460	1	1
463	1	1
466	1	1
469	1	1
472	1	1
475	1	1
478	1	1
481	1	1
484	1	1
487	1	1
491	1	1
493	1	1
496	1	1
500	1	1
504	1	1
507	1	1
508	1	1
509	1	1
510	1	1
			MISSING_ELSE
516	1	1
517	1	1
519	1	1
520	1	1
			MISSING_ELSE
526	1	1
527	1	1
532	1	1
533		unreachable
534		unreachable
			MISSING_ELSE
540	1	1
541	1	1
542	1	1
549	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
			MISSING_ELSE
567	1	1
572	1	1
575	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
			MISSING_ELSE
587	1	1
592	1	1
595	1	1
596	1	1
597	1	1
598	1	1
599	1	1
600	1	1
601	1	1
			MISSING_ELSE
608	1	1
613	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
			MISSING_ELSE
628	1	1
630	1	1
631	1	1
640	1	1
641	1	1
642	1	1
			MISSING_ELSE
653	1	1
654	1	1
656	1	1
657	1	1
			MISSING_ELSE
662	1	1
663	1	1
681	1	1
682	1	1
683	1	1
684	1	1
			MISSING_ELSE
689	1	1
690	1	1
692	1	1
694	1	1
697	1	1
700	1	1
703	1	1
706	1	1
709	1	1
712	1	1
713	1	1
717	1	1
725	1	1
726	1	1
730	1	1
731	1	1
732	1	1
			MISSING_ELSE
763	1	1
769	1	1
800	1	1
808	1	1
809	1	1
811	1	1
818	1	1
865	1	1
907	3	3

---

Cond Coverage for Module : keymgr_ctrl

	Total	Covered	Percent
Conditions	212	208	98.11
Logical	212	208	98.11
Non-Logical	0	0
Event	0	0

 LINE       150
 EXPRESSION (op_i == OpAdvance)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (op_i == OpGenId)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (op_i == OpGenSwOut)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (op_i == OpGenHwOut)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION (gen_id_op | gen_sw_op | gen_hw_op)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (op_start_i & adv_op & en_i)
             -----1----   ---2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T39,T7
1	1	1	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (op_start_i & gen_hw_op & en_i)
             -----1----   ----2----   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T6,T7
1	1	1	Covered	T1,T2,T3

 LINE       169
 EXPRESSION ((op_start_i & dis_op) | ((!en_i)))
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T40,T41

 LINE       169
 SUB-EXPRESSION (op_start_i & dis_op)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T40,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T40,T41

 LINE       185
 EXPRESSION (op_req & adv_op)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (op_req & dis_op)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T40,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T40,T41

 LINE       187
 EXPRESSION (op_req & gen_id_op)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       188
 EXPRESSION (op_req & (gen_sw_op | gen_hw_op))
             ---1--   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       188
 SUB-EXPRESSION (gen_sw_op | gen_hw_op)
                 ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T5,T4
1	1	1	Covered	T1,T2,T5

 LINE       202
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T31,T33
1	0	Covered	T1,T2,T3

 LINE       230
 EXPRESSION (wipe_req ? KeyUpdateWipe : (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       230
 SUB-EXPRESSION (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (init_o ? KeyUpdateRoot : op_update_sel)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (prng_en_dis_inv_set ? 2'b11 : (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q))
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       243
 SUB-EXPRESSION (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (random_req | wipe_req | prng_en_dis_inv_q[0])
             -----1----   ----2---   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T5
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (advance_sel ? cdi_cnt : op_cdi_sel_i)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[0]}}) : key_state_q[cdi_sel_o][0])
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[1]}}) : key_state_q[cdi_sel_o][1])
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       333
 EXPRESSION (root_key_i.creator_root_key_share0_valid && root_key_i.creator_root_key_share1_valid)
             --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       346
 EXPRESSION (op_req ? cnt[0] : '0)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       389
 EXPRESSION ((adv_op || dis_op) ? kmac_data_i : key_state_q[cdi_sel_o])
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       389
 SUB-EXPRESSION (adv_op || dis_op)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T16,T40,T41
1	0	Covered	T1,T2,T5

 LINE       408
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       408
 EXPRESSION (op_update | random_req)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       444
 EXPRESSION (op_ack & adv_req & ((~op_err)))
             ---1--   ---2---   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T3,T5,T4
1	1	1	Covered	T1,T2,T5

 LINE       445
 EXPRESSION (op_ack & dis_req)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T40,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T40,T41

 LINE       504
 EXPRESSION (op_start_i & ((~advance_sel)))
             -----1----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       532
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       542
 EXPRESSION ((en_i && root_key_valid_q) ? StCtrlInit : StCtrlWipe)
             -------------1------------

-1-	Status	Tests
0	Covered	T32,T42,T43
1	Covered	T1,T2,T3

 LINE       542
 SUB-EXPRESSION (en_i && root_key_valid_q)
                 --1-    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T32,T42,T43
1	1	Covered	T1,T2,T3

 LINE       552
 EXPRESSION (advance_sel ? Creator : Disable)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       553
 EXPRESSION (op_start_i & ( ~ (advance_sel | disable_sel) ))
             -----1----   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       553
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T39,T41
1	0	Covered	T1,T2,T3

 LINE       555
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T31,T8
1	0	Covered	T16,T39,T47

 LINE       572
 EXPRESSION (disable_sel ? Disable : (advance_sel ? OwnerInt : Creator))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T47,T48,T49

 LINE       572
 SUB-EXPRESSION (advance_sel ? OwnerInt : Creator)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       575
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T33,T50,T51
1	0	Covered	T47,T48,T49

 LINE       592
 EXPRESSION (disable_sel ? Disable : (advance_sel ? Owner : OwnerInt))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T52,T47

 LINE       592
 SUB-EXPRESSION (advance_sel ? Owner : OwnerInt)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       595
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T19,T53,T54
1	0	Covered	T4,T47,T48

 LINE       613
 EXPRESSION ((disable_sel | advance_sel) ? Disable : Owner)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T5,T4,T14

 LINE       613
 SUB-EXPRESSION (disable_sel | advance_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T5,T4,T14
1	0	Covered	T16,T40,T55

 LINE       615
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T56,T57
1	0	Covered	T58,T59,T60

 LINE       617
 EXPRESSION (adv_state || dis_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T16,T40,T55
1	0	Covered	T5,T4,T14

 LINE       656
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T4,T14
0	1	Covered	T20,T28,T35
1	0	Covered	T61,T58,T62

 LINE       730
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       763
 EXPRESSION ((adv_en_o & ( ~ (advance_sel | disable_sel) )) | (gen_en_o & ((~gen_op))))
             -----------------------1----------------------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T20,T29
1	0	Covered	T8,T21,T22

 LINE       763
 SUB-EXPRESSION (adv_en_o & ( ~ (advance_sel | disable_sel) ))
                 ----1---   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T21,T22

 LINE       763
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       763
 SUB-EXPRESSION (gen_en_o & ((~gen_op)))
                 ----1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T19,T20,T29

 LINE       769
 EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & invalid) ? KeyUpdateKmac : (((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & invalid)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T13

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       769
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T31,T33

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & op_fault_err)
                 ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T31
1	0	Covered	T1,T2,T5
1	1	Covered	T3,T31,T33

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       769
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T14

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & disabled)
                 ----------1---------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T4,T14

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       769
 SUB-EXPRESSION (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))
                 ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & op_err)
                 ----------1---------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       800
 EXPRESSION ((state_d != state_q) & (state_d inside {StCtrlRootKey, StCtrlCreatorRootKey, StCtrlOwnerIntKey, StCtrlOwnerKey}))
             ----------1---------   --------------------------------------------2--------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       800
 SUB-EXPRESSION (state_d != state_q)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       818
 EXPRESSION (vld_state_change_q & ((!adv_op)))
             ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       820
 EXPRESSION (disabled | (initialized & ((~en_i))))
             ----1---   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T39
1	0	Covered	T5,T4,T14

 LINE       820
 SUB-EXPRESSION (initialized & ((~en_i)))
                 -----1-----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T39

 LINE       820
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Not Covered

---

FSM Coverage for Module : keymgr_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	19	19	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlCreatorRootKey	561	Covered	T1,T2,T5
StCtrlDisabled	558	Covered	T5,T4,T14
StCtrlEntropyReseed	510	Covered	T1,T2,T3
StCtrlInit	542	Covered	T1,T2,T3
StCtrlInvalid	641	Covered	T1,T3,T4
StCtrlOwnerIntKey	581	Covered	T1,T2,T5
StCtrlOwnerKey	601	Covered	T1,T2,T5
StCtrlRandom	520	Covered	T1,T2,T3
StCtrlReset	495	Covered	T1,T2,T3
StCtrlRootKey	534	Covered	T1,T2,T3
StCtrlWipe	508	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StCtrlCreatorRootKey->StCtrlDisabled	578	Covered	T48,T63,T64
StCtrlCreatorRootKey->StCtrlOwnerIntKey	581	Covered	T1,T2,T5
StCtrlCreatorRootKey->StCtrlWipe	576	Covered	T33,T50,T51
StCtrlDisabled->StCtrlWipe	657	Covered	T20,T61,T58
StCtrlEntropyReseed->StCtrlRandom	520	Covered	T1,T2,T3
StCtrlInit->StCtrlCreatorRootKey	561	Covered	T1,T2,T5
StCtrlInit->StCtrlDisabled	558	Covered	T16,T41,T6
StCtrlInit->StCtrlWipe	556	Covered	T3,T16,T31
StCtrlOwnerIntKey->StCtrlDisabled	598	Covered	T52,T7,T65
StCtrlOwnerIntKey->StCtrlOwnerKey	601	Covered	T1,T2,T5
StCtrlOwnerIntKey->StCtrlWipe	596	Covered	T4,T19,T47
StCtrlOwnerKey->StCtrlDisabled	618	Covered	T5,T4,T14
StCtrlOwnerKey->StCtrlWipe	616	Covered	T1,T56,T57
StCtrlRandom->StCtrlRootKey	534	Covered	T1,T2,T3
StCtrlReset->StCtrlEntropyReseed	510	Covered	T1,T2,T3
StCtrlReset->StCtrlWipe	508	Covered	T11,T66,T12
StCtrlRootKey->StCtrlInit	542	Covered	T1,T2,T3
StCtrlRootKey->StCtrlWipe	542	Covered	T32,T42,T43
StCtrlWipe->StCtrlInvalid	641	Covered	T1,T3,T4

---

Branch Coverage for Module : keymgr_ctrl

	Line No.	Total	Covered	Percent
Branches		97	97	100.00
TERNARY	230	4	4	100.00
TERNARY	243	3	3	100.00
TERNARY	277	2	2	100.00
TERNARY	346	2	2	100.00
TERNARY	433	2	2	100.00
TERNARY	769	6	6	100.00
TERNARY	281	2	2	100.00
TERNARY	281	2	2	100.00
IF	248	2	2	100.00
IF	261	2	2	100.00
IF	264	2	2	100.00
IF	290	2	2	100.00
CASE	355	7	7	100.00
CASE	493	39	39	100.00
IF	681	3	3	100.00
CASE	692	9	9	100.00
IF	726	4	4	100.00
IF	808	2	2	100.00
IF	907	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	230	(wipe_req) ? 
-2-:	230	(random_req) ? 
-3-:	230	(init_o) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T3,T4
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	(prng_en_dis_inv_set) ? 
-2-:	243	(prng_reseed_done_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	277	(advance_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	769	(((op_ack | op_update) & invalid)) ? 
-2-:	769	(((op_ack | op_update) & op_fault_err)) ? 
-3-:	769	(((op_ack | op_update) & disabled)) ? 
-4-:	769	(((op_ack | op_update) & op_err)) ? 
-5-:	769	((op_ack | op_update)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T11,T12,T13
0	1	-	-	-	Covered	T3,T31,T33
0	0	1	-	-	Covered	T5,T4,T14
0	0	0	1	-	Covered	T1,T2,T5
0	0	0	0	1	Covered	T1,T2,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	(invalid_stage_sel_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	(invalid_stage_sel_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	261	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	264	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	case (update_sel)
-2-:	367	if (root_key_valid_q)
-3-:	389	((adv_op || dis_op)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
KeyUpdateRandom	-	-	Covered	T1,T2,T3
KeyUpdateRoot	1	-	Covered	T1,T2,T3
KeyUpdateRoot	0	-	Covered	T32,T42,T43
KeyUpdateKmac	-	1	Covered	T1,T2,T5
KeyUpdateKmac	-	0	Covered	T1,T2,T5
KeyUpdateWipe	-	-	Covered	T1,T3,T4
default	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	case (state_q)
-2-:	507	if (inv_state)
-3-:	509	if (advance_sel)
-4-:	519	if (prng_reseed_ack_i)
-5-:	532	if ((int'(cnt) == (EntropyRounds - 1)))
-6-:	542	((en_i && root_key_valid_q)) ? 
-7-:	552	(advance_sel) ? 
-8-:	555	if (((!en_i) || inv_state))
-9-:	557	if (dis_state)
-10-:	560	if (adv_state)
-11-:	572	(disable_sel) ? 
-12-:	572	(advance_sel) ? 
-13-:	575	if (((!en_i) || inv_state))
-14-:	577	if (dis_state)
-15-:	580	if (adv_state)
-16-:	592	(disable_sel) ? 
-17-:	592	(advance_sel) ? 
-18-:	595	if (((!en_i) || inv_state))
-19-:	597	if (dis_state)
-20-:	600	if (adv_state)
-21-:	613	((disable_sel | advance_sel)) ? 
-22-:	615	if (((!en_i) || inv_state))
-23-:	617	if ((adv_state || dis_state))
-24-:	640	if ((!op_start_i))
-25-:	656	if (((!en_i) || inv_state))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	Status	Tests
StCtrlReset	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T66,T12
StCtrlReset	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlReset	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlEntropyReseed	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlEntropyReseed	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlRandom	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable	T1,T2,T3
StCtrlRandom	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlRootKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlRootKey	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T42,T43
StCtrlInit	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlInit	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlInit	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T31
StCtrlInit	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T41,T6
StCtrlInit	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlInit	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T47,T48,T49
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T50,T51
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T63,T64
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlCreatorRootKey	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T52,T47
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T19,T47
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T52,T7,T65
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T5
StCtrlOwnerIntKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T5
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T4,T14
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T5
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T56,T57
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T5,T4,T14
StCtrlOwnerKey	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T5
StCtrlWipe	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
StCtrlWipe	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T16,T39
StCtrlDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T61,T58
StCtrlDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T4,T14
StCtrlInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	681	if ((!rst_ni))
-2-:	683	if (update_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	692	case (state_q)

Branches:

-1-	Status	Tests
StCtrlReset StCtrlEntropyReseed StCtrlRandom	Covered	T1,T2,T3
StCtrlRootKey StCtrlInit	Covered	T1,T2,T3
StCtrlCreatorRootKey	Covered	T1,T2,T5
StCtrlOwnerIntKey	Covered	T1,T2,T5
StCtrlOwnerKey	Covered	T1,T2,T5
StCtrlDisabled	Covered	T5,T4,T14
StCtrlWipe	Covered	T1,T3,T4
StCtrlInvalid	Covered	T1,T3,T4
default	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	726	if (op_done_o)
-2-:	730	((|{error_o, fault_o})) ? 
-3-:	731	if (op_start_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	907	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntZero_A	23984568	30344	0	0
DataEnDis_A	23722732	29788	0	0
DataEn_A	23722732	6403825	0	0
GeneralLegalCommands_A	24375491	27978	0	0
InitLegalCommands_A	24375491	1269437	0	0
LoadKey_A	24256326	17424660	0	0
OwnerLegalCommands_A	24375491	1365623	0	0
SameErrCnt_A	882	882	0	0
SecCmCFILinear_A	24375491	0	0	4809
StageDisableSel_A	24375491	932308	0	0
u_state_regs_A	24375491	24208297	0	0

CntZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23984568	30344	0	0
T1	4647	15	0	0
T2	40432	18	0	0
T3	10023	24	0	0
T4	102733	180	0	0
T5	3783	21	0	0
T14	3310	16	0	0
T15	5856	21	0	0
T16	211557	233	0	0
T17	3417	17	0	0
T18	4903	34	0	0

DataEnDis_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23722732	29788	0	0
T1	4647	15	0	0
T2	34177	15	0	0
T3	10023	24	0	0
T4	102733	180	0	0
T5	3783	21	0	0
T14	3310	16	0	0
T15	5856	21	0	0
T16	211557	233	0	0
T17	2521	12	0	0
T18	4903	34	0	0

DataEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23722732	6403825	0	0
T1	4647	437	0	0
T2	34177	14087	0	0
T3	10023	0	0	0
T4	102733	26308	0	0
T5	3783	476	0	0
T14	3310	85	0	0
T15	5856	1334	0	0
T16	211557	53894	0	0
T17	2521	675	0	0
T18	4903	1192	0	0
T67	0	4443	0	0

GeneralLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24375491	27978	0	0
T45	0	254	0	0
T53	4650	0	0	0
T56	14972	0	0	0
T63	146300	553	0	0
T65	14688	1359	0	0
T68	0	131	0	0
T69	0	528	0	0
T70	0	42	0	0
T71	0	57	0	0
T72	0	42	0	0
T73	0	351	0	0
T74	0	149	0	0
T75	84561	0	0	0
T76	27786	0	0	0
T77	4431	0	0	0
T78	8702	0	0	0
T79	3392	0	0	0
T80	949	0	0	0

InitLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24375491	1269437	0	0
T1	10095	18	0	0
T2	40432	4638	0	0
T3	10023	0	0	0
T4	102733	2949	0	0
T5	3783	37	0	0
T14	3310	16	0	0
T15	5856	135	0	0
T16	211557	9078	0	0
T17	3417	319	0	0
T18	4903	21	0	0
T67	0	624	0	0

LoadKey_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24256326	17424660	0	0
T1	10095	878	0	0
T2	40432	36230	0	0
T3	10023	2575	0	0
T4	102733	82658	0	0
T5	3783	1583	0	0
T14	3310	395	0	0
T15	5856	4117	0	0
T16	211557	142928	0	0
T17	3417	2025	0	0
T18	4903	2198	0	0

OwnerLegalCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24375491	1365623	0	0
T4	102733	7315	0	0
T5	3783	120	0	0
T14	3310	42	0	0
T15	5856	333	0	0
T16	211557	13004	0	0
T17	3417	0	0	0
T18	4903	168	0	0
T26	0	13659	0	0
T32	11897	0	0	0
T67	16111	1394	0	0
T81	9202	600	0	0
T82	0	42	0	0

SameErrCnt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	882	882	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24375491	0	0	4809

StageDisableSel_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24375491	932308	0	0
T1	10095	1057	0	0
T2	40432	33	0	0
T3	10023	244	0	0
T4	102733	5425	0	0
T5	3783	331	0	0
T14	3310	36	0	0
T15	5856	20	0	0
T16	211557	6685	0	0
T17	3417	20	0	0
T18	4903	77	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24375491	24208297	0	0
T1	10095	9957	0	0
T2	40432	40372	0	0
T3	10023	9881	0	0
T4	102733	102033	0	0
T5	3783	3727	0	0
T14	3310	3258	0	0
T15	5856	5756	0	0
T16	211557	210701	0	0
T17	3417	3333	0	0
T18	4903	4811	0	0