Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3501625	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

615977

1

T1

241

T2

241

T3

5743

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3704570	1			T1	681		T2	602		T3	27335
values[0x0]	205127	1			T1	64		T2	68		T3	2166
values[0x1]	207905	1			T1	62		T2	69		T3	2043

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2392726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1724876

1

T1

372

T2

355

T3

13684

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11825	1			T1	13		T2	4		T3	129
valid_sources[0x01]	14109	1			T3	137		T4	532		T5	1
valid_sources[0x02]	14045	1			T1	3		T2	3		T3	119
valid_sources[0x03]	15128	1			T1	1		T2	2		T3	110
valid_sources[0x04]	12177	1			T1	9		T2	2		T3	135
valid_sources[0x05]	12366	1			T2	5		T3	135		T4	564
valid_sources[0x06]	11925	1			T1	3		T2	2		T3	103
valid_sources[0x07]	15325	1			T2	3		T3	92		T4	524
valid_sources[0x08]	18917	1			T2	6		T3	123		T4	513
valid_sources[0x09]	13893	1			T1	8		T2	4		T3	122
valid_sources[0x0a]	13178	1			T1	6		T2	3		T3	123
valid_sources[0x0b]	12455	1			T1	2		T2	2		T3	142
valid_sources[0x0c]	17409	1			T1	4		T2	1		T3	121
valid_sources[0x0d]	13841	1			T1	3		T2	5		T3	135
valid_sources[0x0e]	38854	1			T2	3		T3	127		T4	546
valid_sources[0x0f]	11915	1			T1	2		T3	108		T4	522
valid_sources[0x10]	17314	1			T1	1		T2	1		T3	115
valid_sources[0x11]	17772	1			T1	12		T2	3		T3	134
valid_sources[0x12]	12033	1			T1	1		T3	132		T4	541
valid_sources[0x13]	12845	1			T2	4		T3	117		T4	539
valid_sources[0x14]	12625	1			T1	1		T2	1		T3	120
valid_sources[0x15]	12904	1			T2	4		T3	140		T4	560
valid_sources[0x16]	14845	1			T1	2		T2	7		T3	91
valid_sources[0x17]	14836	1			T2	3		T3	115		T4	592
valid_sources[0x18]	12130	1			T2	5		T3	133		T4	500
valid_sources[0x19]	12737	1			T1	4		T2	2		T3	126
valid_sources[0x1a]	12460	1			T2	3		T3	120		T4	551
valid_sources[0x1b]	14934	1			T1	3		T3	121		T4	512
valid_sources[0x1c]	13190	1			T2	3		T3	118		T4	519
valid_sources[0x1d]	12446	1			T1	5		T2	5		T3	123
valid_sources[0x1e]	16106	1			T1	1		T2	3		T3	115
valid_sources[0x1f]	13892	1			T1	3		T2	5		T3	124
valid_sources[0x20]	24709	1			T1	10		T2	1		T3	134
valid_sources[0x21]	14651	1			T1	5		T2	3		T3	113
valid_sources[0x22]	12225	1			T1	15		T2	2		T3	121
valid_sources[0x23]	20864	1			T2	1		T3	127		T4	540
valid_sources[0x24]	14116	1			T1	2		T2	2		T3	107
valid_sources[0x25]	16771	1			T3	107		T4	575		T5	1
valid_sources[0x26]	13188	1			T2	2		T3	129		T4	518
valid_sources[0x27]	13103	1			T1	11		T2	2		T3	100
valid_sources[0x28]	12212	1			T2	4		T3	136		T4	575
valid_sources[0x29]	18544	1			T1	3		T2	2		T3	86
valid_sources[0x2a]	12587	1			T1	16		T2	5		T3	108
valid_sources[0x2b]	55117	1			T1	3		T3	108		T4	546
valid_sources[0x2c]	11541	1			T1	4		T2	1		T3	107
valid_sources[0x2d]	13378	1			T1	2		T2	1		T3	139
valid_sources[0x2e]	12269	1			T3	94		T4	538		T5	1
valid_sources[0x2f]	11822	1			T2	5		T3	127		T4	542
valid_sources[0x30]	12299	1			T2	4		T3	125		T4	536
valid_sources[0x31]	12148	1			T1	4		T2	1		T3	117
valid_sources[0x32]	16843	1			T1	2		T2	2		T3	147
valid_sources[0x33]	12645	1			T1	1		T2	6		T3	126
valid_sources[0x34]	14802	1			T1	6		T2	4		T3	118
valid_sources[0x35]	26915	1			T1	3		T2	2		T3	114
valid_sources[0x36]	13969	1			T1	6		T2	5		T3	114
valid_sources[0x37]	13645	1			T1	4		T2	1		T3	126
valid_sources[0x38]	12317	1			T2	3		T3	122		T4	495
valid_sources[0x39]	20022	1			T1	3		T2	2		T3	148
valid_sources[0x3a]	12011	1			T1	5		T2	4		T3	121
valid_sources[0x3b]	12349	1			T2	2		T3	125		T4	524
valid_sources[0x3c]	12840	1			T2	4		T3	126		T4	543
valid_sources[0x3d]	11858	1			T1	4		T2	9		T3	123
valid_sources[0x3e]	14898	1			T1	6		T2	2		T3	107
valid_sources[0x3f]	14318	1			T1	3		T2	2		T3	121
valid_sources[0x40]	20665	1			T2	2		T3	121		T4	546
valid_sources[0x41]	21878	1			T1	20		T2	2		T3	123
valid_sources[0x42]	35064	1			T1	1		T2	2		T3	125
valid_sources[0x43]	11850	1			T2	3		T3	131		T4	526
valid_sources[0x44]	13228	1			T1	3		T2	4		T3	113
valid_sources[0x45]	16311	1			T1	3		T2	5		T3	127
valid_sources[0x46]	13861	1			T1	3		T2	4		T3	133
valid_sources[0x47]	15441	1			T1	14		T2	3		T3	144
valid_sources[0x48]	14015	1			T1	1		T2	2		T3	132
valid_sources[0x49]	12982	1			T1	2		T2	2		T3	129
valid_sources[0x4a]	11948	1			T1	9		T2	5		T3	135
valid_sources[0x4b]	12880	1			T1	2		T2	2		T3	105
valid_sources[0x4c]	13279	1			T1	10		T2	2		T3	129
valid_sources[0x4d]	18619	1			T1	9		T2	2		T3	115
valid_sources[0x4e]	13442	1			T1	8		T2	1		T3	125
valid_sources[0x4f]	12638	1			T1	2		T3	129		T4	538
valid_sources[0x50]	11718	1			T1	4		T2	1		T3	127
valid_sources[0x51]	12475	1			T1	1		T2	2		T3	122
valid_sources[0x52]	11595	1			T1	1		T2	5		T3	135
valid_sources[0x53]	12244	1			T1	2		T2	5		T3	120
valid_sources[0x54]	12318	1			T1	3		T2	2		T3	143
valid_sources[0x55]	13888	1			T1	1		T2	1		T3	122
valid_sources[0x56]	12437	1			T1	2		T2	7		T3	157
valid_sources[0x57]	11783	1			T1	5		T2	2		T3	103
valid_sources[0x58]	12776	1			T2	3		T3	145		T4	506
valid_sources[0x59]	15575	1			T2	1		T3	139		T4	527
valid_sources[0x5a]	12591	1			T1	1		T2	2		T3	129
valid_sources[0x5b]	19572	1			T3	101		T4	534		T5	5
valid_sources[0x5c]	16157	1			T1	2		T3	123		T4	515
valid_sources[0x5d]	29094	1			T1	1		T2	1		T3	126
valid_sources[0x5e]	12992	1			T1	4		T2	3		T3	152
valid_sources[0x5f]	15327	1			T1	1		T2	4		T3	118
valid_sources[0x60]	12940	1			T1	5		T2	2		T3	135
valid_sources[0x61]	12416	1			T1	6		T2	2		T3	122
valid_sources[0x62]	15662	1			T1	1		T2	3		T3	134
valid_sources[0x63]	15664	1			T3	114		T4	567		T5	5
valid_sources[0x64]	17381	1			T1	2		T2	3		T3	118
valid_sources[0x65]	16006	1			T2	3		T3	117		T4	546
valid_sources[0x66]	12231	1			T1	2		T2	2		T3	124
valid_sources[0x67]	12142	1			T2	3		T3	118		T4	544
valid_sources[0x68]	16185	1			T1	7		T2	4		T3	148
valid_sources[0x69]	13586	1			T1	1		T2	4		T3	134
valid_sources[0x6a]	28118	1			T2	1		T3	130		T4	582
valid_sources[0x6b]	12394	1			T1	5		T3	123		T4	555
valid_sources[0x6c]	12894	1			T1	3		T2	3		T3	134
valid_sources[0x6d]	12361	1			T1	7		T2	7		T3	120
valid_sources[0x6e]	17992	1			T2	5		T3	105		T4	534
valid_sources[0x6f]	13931	1			T1	3		T2	4		T3	130
valid_sources[0x70]	12321	1			T2	1		T3	132		T4	558
valid_sources[0x71]	11415	1			T1	4		T2	2		T3	135
valid_sources[0x72]	13278	1			T1	14		T2	3		T3	115
valid_sources[0x73]	33338	1			T2	2		T3	121		T4	515
valid_sources[0x74]	11811	1			T1	3		T2	3		T3	115
valid_sources[0x75]	11687	1			T1	2		T2	3		T3	128
valid_sources[0x76]	13034	1			T1	4		T2	6		T3	131
valid_sources[0x77]	12565	1			T1	2		T2	2		T3	114
valid_sources[0x78]	12200	1			T1	8		T2	3		T3	109
valid_sources[0x79]	12540	1			T2	2		T3	146		T4	539
valid_sources[0x7a]	21588	1			T1	7		T3	94		T4	509
valid_sources[0x7b]	12051	1			T1	7		T2	5		T3	118
valid_sources[0x7c]	14500	1			T1	4		T2	1		T3	119
valid_sources[0x7d]	13352	1			T1	1		T2	4		T3	120
valid_sources[0x7e]	14525	1			T2	2		T3	107		T4	522
valid_sources[0x7f]	14973	1			T1	2		T2	2		T3	146
valid_sources[0x80]	20586	1			T1	1		T2	5		T3	119

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

332840

1

T1

202

T2

206

T3

2938

values[0x0]

all_enables

biggest_size

148828

1

T1

25

T2

20

T3

1504

values[0x1]

all_enables

biggest_size

134309

1

T1

14

T2

15

T3

1301