Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
23916627 |
23757412 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23916627 |
23757412 |
0 |
0 |
T1 |
11051 |
10960 |
0 |
0 |
T2 |
9018 |
8920 |
0 |
0 |
T3 |
295867 |
294473 |
0 |
0 |
T4 |
132440 |
132381 |
0 |
0 |
T5 |
2381 |
2330 |
0 |
0 |
T14 |
839 |
763 |
0 |
0 |
T15 |
2426 |
2331 |
0 |
0 |
T16 |
11015 |
10919 |
0 |
0 |
T17 |
1144 |
1091 |
0 |
0 |
T18 |
7363 |
7269 |
0 |
0 |