Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25830129	17151	0	0
attest_sw_binding_0_rd_A	25830129	3572	0	0
attest_sw_binding_1_rd_A	25830129	3665	0	0
attest_sw_binding_2_rd_A	25830129	3867	0	0
attest_sw_binding_3_rd_A	25830129	3902	0	0
attest_sw_binding_4_rd_A	25830129	3594	0	0
attest_sw_binding_5_rd_A	25830129	3686	0	0
attest_sw_binding_6_rd_A	25830129	3726	0	0
attest_sw_binding_7_rd_A	25830129	3610	0	0
intr_enable_rd_A	25830129	4045	0	0
key_version_rd_A	25830129	3693	0	0
max_creator_key_ver_regwen_rd_A	25830129	3680	0	0
max_owner_int_key_ver_regwen_rd_A	25830129	3630	0	0
max_owner_key_ver_regwen_rd_A	25830129	3853	0	0
reseed_interval_regwen_rd_A	25830129	3700	0	0
salt_0_rd_A	25830129	3641	0	0
salt_1_rd_A	25830129	3581	0	0
salt_2_rd_A	25830129	3699	0	0
salt_3_rd_A	25830129	3895	0	0
salt_4_rd_A	25830129	3789	0	0
salt_5_rd_A	25830129	3824	0	0
salt_6_rd_A	25830129	3629	0	0
salt_7_rd_A	25830129	3696	0	0
sealing_sw_binding_0_rd_A	25830129	3547	0	0
sealing_sw_binding_1_rd_A	25830129	3561	0	0
sealing_sw_binding_2_rd_A	25830129	3676	0	0
sealing_sw_binding_3_rd_A	25830129	3773	0	0
sealing_sw_binding_4_rd_A	25830129	3616	0	0
sealing_sw_binding_5_rd_A	25830129	3744	0	0
sealing_sw_binding_6_rd_A	25830129	3621	0	0
sealing_sw_binding_7_rd_A	25830129	3876	0	0
sideload_clear_rd_A	25830129	3791	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	17151	0	0
T26	38619	0	0	0
T64	35270	528	0	0
T82	0	183	0	0
T102	0	162	0	0
T103	0	725	0	0
T109	250122	0	0	0
T111	0	447	0	0
T112	0	25	0	0
T113	0	171	0	0
T114	0	1225	0	0
T115	0	710	0	0
T117	0	308	0	0
T118	977	0	0	0
T119	1954	0	0	0
T120	14116	0	0	0
T121	115698	0	0	0
T122	103784	0	0	0
T123	5119	0	0	0
T124	7052	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3572	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	74	0	0
T107	0	42	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	1	0	0
T185	0	43	0	0
T186	0	60	0	0
T187	0	44	0	0
T188	0	21	0	0
T189	0	41	0	0
T190	0	55	0	0
T191	0	16	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3665	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	47	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	11	0	0
T185	0	51	0	0
T186	0	60	0	0
T187	0	85	0	0
T188	0	36	0	0
T189	0	24	0	0
T190	0	43	0	0
T191	0	20	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0
T197	0	1	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3867	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	27	0	0
T107	0	29	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	19	0	0
T185	0	42	0	0
T186	0	62	0	0
T187	0	95	0	0
T188	0	38	0	0
T189	0	26	0	0
T190	0	67	0	0
T191	0	30	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3902	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	42	0	0
T107	0	39	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	9	0	0
T185	0	56	0	0
T186	0	55	0	0
T187	0	69	0	0
T188	0	21	0	0
T189	0	38	0	0
T190	0	52	0	0
T191	0	20	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3594	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	34	0	0
T107	0	41	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	11	0	0
T185	0	16	0	0
T186	0	57	0	0
T187	0	48	0	0
T188	0	23	0	0
T189	0	27	0	0
T190	0	56	0	0
T191	0	12	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3686	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	28	0	0
T107	0	53	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	9	0	0
T185	0	46	0	0
T186	0	55	0	0
T187	0	44	0	0
T188	0	44	0	0
T189	0	14	0	0
T190	0	78	0	0
T191	0	28	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3726	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	38	0	0
T107	0	59	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	15	0	0
T185	0	15	0	0
T186	0	44	0	0
T187	0	64	0	0
T188	0	26	0	0
T189	0	36	0	0
T190	0	67	0	0
T191	0	44	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3610	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	51	0	0
T107	0	39	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	10	0	0
T185	0	18	0	0
T186	0	47	0	0
T187	0	73	0	0
T188	0	25	0	0
T189	0	50	0	0
T190	0	65	0	0
T191	0	29	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	4045	0	0
T28	17434	0	0	0
T69	0	44	0	0
T70	0	15	0	0
T96	12144	0	0	0
T102	33351	70	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T185	0	54	0	0
T186	0	39	0	0
T187	0	77	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0
T198	0	18	0	0
T199	0	7	0	0
T200	0	18	0	0
T201	0	12	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3693	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	45	0	0
T107	0	51	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	5	0	0
T185	0	33	0	0
T186	0	70	0	0
T187	0	54	0	0
T188	0	37	0	0
T189	0	42	0	0
T190	0	54	0	0
T191	0	18	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3680	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	42	0	0
T107	0	54	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	3	0	0
T185	0	48	0	0
T186	0	60	0	0
T187	0	62	0	0
T188	0	35	0	0
T189	0	40	0	0
T190	0	53	0	0
T191	0	31	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3630	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	39	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	18	0	0
T185	0	26	0	0
T186	0	64	0	0
T187	0	75	0	0
T188	0	14	0	0
T189	0	22	0	0
T190	0	73	0	0
T191	0	27	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0
T202	0	1	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3853	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	34	0	0
T107	0	45	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	8	0	0
T185	0	24	0	0
T186	0	63	0	0
T187	0	47	0	0
T188	0	20	0	0
T189	0	36	0	0
T190	0	63	0	0
T191	0	28	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3700	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	28	0	0
T107	0	44	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	14	0	0
T185	0	34	0	0
T186	0	48	0	0
T187	0	52	0	0
T188	0	56	0	0
T189	0	18	0	0
T190	0	57	0	0
T191	0	44	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3641	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	35	0	0
T107	0	35	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	11	0	0
T185	0	20	0	0
T186	0	34	0	0
T187	0	71	0	0
T188	0	27	0	0
T189	0	37	0	0
T190	0	54	0	0
T191	0	6	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3581	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	28	0	0
T107	0	52	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	14	0	0
T185	0	43	0	0
T186	0	56	0	0
T187	0	50	0	0
T188	0	45	0	0
T189	0	32	0	0
T190	0	44	0	0
T191	0	24	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3699	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	35	0	0
T107	0	30	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	12	0	0
T185	0	20	0	0
T186	0	35	0	0
T187	0	73	0	0
T188	0	26	0	0
T189	0	37	0	0
T190	0	48	0	0
T191	0	21	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3895	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	30	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	8	0	0
T185	0	43	0	0
T186	0	37	0	0
T187	0	56	0	0
T188	0	19	0	0
T189	0	25	0	0
T190	0	73	0	0
T191	0	27	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0
T203	0	5	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3789	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	18	0	0
T107	0	33	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	3	0	0
T185	0	46	0	0
T186	0	71	0	0
T187	0	63	0	0
T188	0	18	0	0
T189	0	18	0	0
T190	0	61	0	0
T191	0	23	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3824	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	25	0	0
T107	0	44	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	5	0	0
T185	0	32	0	0
T186	0	60	0	0
T187	0	58	0	0
T188	0	26	0	0
T189	0	49	0	0
T190	0	47	0	0
T191	0	35	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3629	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	23	0	0
T107	0	42	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	10	0	0
T185	0	28	0	0
T186	0	60	0	0
T187	0	67	0	0
T188	0	12	0	0
T189	0	37	0	0
T190	0	60	0	0
T191	0	10	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3696	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	18	0	0
T107	0	40	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	9	0	0
T185	0	16	0	0
T186	0	51	0	0
T187	0	52	0	0
T188	0	16	0	0
T189	0	49	0	0
T190	0	57	0	0
T191	0	32	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3547	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	26	0	0
T107	0	34	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	7	0	0
T185	0	35	0	0
T186	0	59	0	0
T187	0	55	0	0
T188	0	13	0	0
T189	0	27	0	0
T190	0	44	0	0
T191	0	16	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3561	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	19	0	0
T107	0	31	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	10	0	0
T185	0	45	0	0
T186	0	59	0	0
T187	0	70	0	0
T188	0	15	0	0
T189	0	28	0	0
T190	0	45	0	0
T191	0	47	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3676	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	41	0	0
T107	0	47	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	7	0	0
T185	0	43	0	0
T186	0	37	0	0
T187	0	91	0	0
T188	0	18	0	0
T189	0	11	0	0
T190	0	85	0	0
T191	0	35	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3773	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	39	0	0
T107	0	55	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	8	0	0
T185	0	28	0	0
T186	0	51	0	0
T187	0	62	0	0
T188	0	20	0	0
T189	0	29	0	0
T190	0	67	0	0
T191	0	31	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3616	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	57	0	0
T107	0	37	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	3	0	0
T185	0	44	0	0
T186	0	52	0	0
T187	0	51	0	0
T188	0	21	0	0
T189	0	28	0	0
T190	0	60	0	0
T191	0	35	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3744	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	54	0	0
T107	0	36	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	8	0	0
T185	0	33	0	0
T186	0	66	0	0
T187	0	76	0	0
T188	0	29	0	0
T189	0	50	0	0
T190	0	62	0	0
T191	0	15	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3621	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	29	0	0
T107	0	54	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	11	0	0
T185	0	25	0	0
T186	0	46	0	0
T187	0	76	0	0
T188	0	19	0	0
T189	0	32	0	0
T190	0	55	0	0
T191	0	27	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3876	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	20	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	11	0	0
T185	0	41	0	0
T186	0	51	0	0
T187	0	65	0	0
T188	0	23	0	0
T189	0	32	0	0
T190	0	50	0	0
T191	0	38	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0
T204	0	5	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25830129	3791	0	0
T28	17434	0	0	0
T96	12144	0	0	0
T102	33351	25	0	0
T107	0	41	0	0
T149	60316	0	0	0
T150	107540	0	0	0
T159	0	7	0	0
T185	0	38	0	0
T186	0	38	0	0
T187	0	77	0	0
T188	0	28	0	0
T189	0	24	0	0
T190	0	38	0	0
T191	0	48	0	0
T192	3236	0	0	0
T193	73192	0	0	0
T194	7117	0	0	0
T195	4964	0	0	0
T196	12944	0	0	0