Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3077455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

604755

1

T1

274

T2

404

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3282053	1			T1	1707		T2	447		T3	1
values[0x0]	198113	1			T1	101		T2	173		T3	6
values[0x1]	202044	1			T1	119		T2	162		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2108276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1573934

1

T1

805

T2

472

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22539	1			T1	11		T2	7		T4	2
valid_sources[0x01]	12369	1			T1	4		T4	2		T5	2
valid_sources[0x02]	12073	1			T1	6		T2	5		T4	4
valid_sources[0x03]	13122	1			T1	2		T2	1		T4	3
valid_sources[0x04]	11351	1			T1	12		T2	2		T4	7
valid_sources[0x05]	10847	1			T1	11		T2	3		T4	4
valid_sources[0x06]	11358	1			T1	10		T2	3		T4	7
valid_sources[0x07]	13674	1			T1	1		T4	6		T5	6
valid_sources[0x08]	21187	1			T1	9		T2	8		T4	6
valid_sources[0x09]	9705	1			T1	11		T4	5		T13	4
valid_sources[0x0a]	10517	1			T1	3		T2	1		T4	3
valid_sources[0x0b]	14380	1			T1	2		T4	6		T5	6
valid_sources[0x0c]	11060	1			T1	7		T4	7		T5	2
valid_sources[0x0d]	10308	1			T1	9		T2	8		T3	1
valid_sources[0x0e]	12915	1			T1	9		T2	2		T4	3
valid_sources[0x0f]	14024	1			T1	9		T2	6		T4	4
valid_sources[0x10]	11195	1			T1	7		T2	4		T4	3
valid_sources[0x11]	9970	1			T1	11		T2	3		T4	1
valid_sources[0x12]	10674	1			T1	5		T2	7		T4	2
valid_sources[0x13]	13182	1			T1	8		T2	17		T4	5
valid_sources[0x14]	14520	1			T1	6		T2	3		T4	6
valid_sources[0x15]	12292	1			T1	11		T4	3		T5	1
valid_sources[0x16]	11715	1			T1	7		T4	5		T13	7
valid_sources[0x17]	34857	1			T1	3		T4	2		T5	3
valid_sources[0x18]	11970	1			T1	7		T2	3		T4	2
valid_sources[0x19]	10977	1			T1	8		T4	8		T5	12
valid_sources[0x1a]	13537	1			T1	4		T2	4		T4	3
valid_sources[0x1b]	13128	1			T1	7		T2	1		T4	3
valid_sources[0x1c]	12026	1			T1	4		T4	2		T13	9
valid_sources[0x1d]	10558	1			T1	8		T2	1		T4	3
valid_sources[0x1e]	13674	1			T1	4		T4	5		T5	30
valid_sources[0x1f]	12906	1			T1	11		T2	1		T4	3
valid_sources[0x20]	10529	1			T1	4		T2	1		T4	4
valid_sources[0x21]	10650	1			T1	10		T13	5		T14	44
valid_sources[0x22]	11458	1			T1	5		T4	4		T5	1
valid_sources[0x23]	17184	1			T1	5		T2	4		T4	5
valid_sources[0x24]	11069	1			T1	12		T2	5		T4	3
valid_sources[0x25]	12482	1			T1	9		T2	2		T4	3
valid_sources[0x26]	11584	1			T1	10		T2	8		T4	5
valid_sources[0x27]	13210	1			T1	5		T2	1		T4	2
valid_sources[0x28]	11281	1			T1	2		T4	1		T5	14
valid_sources[0x29]	17716	1			T1	6		T4	4		T5	1
valid_sources[0x2a]	10984	1			T1	8		T2	15		T4	4
valid_sources[0x2b]	10453	1			T1	8		T4	4		T13	5
valid_sources[0x2c]	11899	1			T1	5		T4	2		T5	1
valid_sources[0x2d]	12128	1			T1	5		T4	1		T5	2
valid_sources[0x2e]	11538	1			T1	2		T2	8		T4	4
valid_sources[0x2f]	10431	1			T1	7		T2	4		T4	1
valid_sources[0x30]	24182	1			T1	7		T2	14		T4	5
valid_sources[0x31]	12882	1			T1	6		T2	9		T4	2
valid_sources[0x32]	10725	1			T1	11		T2	1		T4	2
valid_sources[0x33]	12536	1			T1	7		T2	5		T4	2
valid_sources[0x34]	11638	1			T1	9		T2	7		T4	4
valid_sources[0x35]	11111	1			T1	9		T2	2		T4	5
valid_sources[0x36]	10047	1			T1	7		T2	4		T4	2
valid_sources[0x37]	11145	1			T1	6		T4	1		T13	10
valid_sources[0x38]	14896	1			T1	7		T2	7		T4	2
valid_sources[0x39]	18671	1			T1	1		T2	2		T4	5
valid_sources[0x3a]	11226	1			T1	9		T2	2		T4	4
valid_sources[0x3b]	13161	1			T1	9		T4	3		T5	6
valid_sources[0x3c]	62583	1			T1	9		T2	1		T4	4
valid_sources[0x3d]	11083	1			T1	5		T2	2		T4	3
valid_sources[0x3e]	13266	1			T1	7		T2	4		T4	4
valid_sources[0x3f]	12735	1			T1	8		T2	3		T4	2
valid_sources[0x40]	19810	1			T1	5		T4	4		T5	11
valid_sources[0x41]	12260	1			T1	10		T2	3		T4	4
valid_sources[0x42]	11094	1			T1	6		T2	3		T4	7
valid_sources[0x43]	10571	1			T1	4		T2	1		T5	2
valid_sources[0x44]	13379	1			T1	2		T4	2		T13	7
valid_sources[0x45]	12066	1			T1	8		T2	15		T4	2
valid_sources[0x46]	13425	1			T1	12		T2	5		T4	2
valid_sources[0x47]	10504	1			T1	9		T4	1		T5	5
valid_sources[0x48]	10803	1			T1	6		T4	2		T5	3
valid_sources[0x49]	10321	1			T1	7		T2	2		T4	4
valid_sources[0x4a]	12206	1			T1	6		T2	7		T4	6
valid_sources[0x4b]	14076	1			T1	10		T2	4		T4	4
valid_sources[0x4c]	12177	1			T1	11		T4	2		T5	1
valid_sources[0x4d]	15128	1			T1	6		T2	5		T4	1
valid_sources[0x4e]	11410	1			T1	5		T2	1		T4	8
valid_sources[0x4f]	220049	1			T1	7		T2	4		T4	5
valid_sources[0x50]	10567	1			T1	10		T4	4		T5	7
valid_sources[0x51]	22017	1			T1	11		T2	2		T4	3
valid_sources[0x52]	43969	1			T1	7		T4	3		T13	3
valid_sources[0x53]	11504	1			T1	4		T4	5		T5	2
valid_sources[0x54]	12333	1			T1	5		T2	9		T4	2
valid_sources[0x55]	12162	1			T1	9		T2	2		T4	2
valid_sources[0x56]	11058	1			T1	9		T4	3		T13	4
valid_sources[0x57]	10114	1			T1	6		T2	2		T4	3
valid_sources[0x58]	10009	1			T1	3		T2	1		T4	1
valid_sources[0x59]	23037	1			T1	7		T2	3		T3	1
valid_sources[0x5a]	10138	1			T1	7		T2	9		T4	3
valid_sources[0x5b]	11860	1			T1	7		T4	5		T13	6
valid_sources[0x5c]	13038	1			T1	9		T2	5		T4	6
valid_sources[0x5d]	14917	1			T1	4		T2	1		T4	3
valid_sources[0x5e]	13625	1			T1	4		T2	3		T4	2
valid_sources[0x5f]	12367	1			T1	11		T2	4		T4	2
valid_sources[0x60]	50719	1			T1	8		T2	4		T4	4
valid_sources[0x61]	10740	1			T1	9		T2	4		T4	2
valid_sources[0x62]	20302	1			T1	12		T2	5		T4	3
valid_sources[0x63]	11472	1			T1	19		T2	6		T4	8
valid_sources[0x64]	10525	1			T4	5		T5	7		T13	12
valid_sources[0x65]	18053	1			T1	7		T4	7		T13	5
valid_sources[0x66]	12821	1			T1	11		T2	4		T4	4
valid_sources[0x67]	12250	1			T1	6		T2	6		T4	2
valid_sources[0x68]	15381	1			T1	10		T2	9		T4	7
valid_sources[0x69]	11518	1			T1	8		T2	4		T4	5
valid_sources[0x6a]	12759	1			T1	14		T2	4		T4	5
valid_sources[0x6b]	11480	1			T1	3		T2	16		T4	2
valid_sources[0x6c]	11488	1			T1	12		T2	12		T4	1
valid_sources[0x6d]	10958	1			T1	6		T2	5		T4	2
valid_sources[0x6e]	12330	1			T1	1		T4	4		T13	4
valid_sources[0x6f]	10560	1			T1	17		T2	4		T4	1
valid_sources[0x70]	14381	1			T1	12		T2	1		T4	4
valid_sources[0x71]	16476	1			T1	8		T4	5		T13	1
valid_sources[0x72]	19562	1			T1	9		T4	2		T5	10
valid_sources[0x73]	12378	1			T1	8		T4	1		T5	5
valid_sources[0x74]	10967	1			T1	8		T2	2		T4	4
valid_sources[0x75]	12014	1			T1	11		T2	2		T4	2
valid_sources[0x76]	12733	1			T1	8		T2	6		T3	1
valid_sources[0x77]	17572	1			T1	8		T2	7		T4	4
valid_sources[0x78]	14497	1			T1	10		T2	1		T4	1
valid_sources[0x79]	11367	1			T1	13		T4	1		T13	3
valid_sources[0x7a]	10659	1			T1	7		T2	6		T4	3
valid_sources[0x7b]	10305	1			T1	9		T2	3		T4	3
valid_sources[0x7c]	12415	1			T1	10		T2	3		T4	5
valid_sources[0x7d]	11136	1			T1	6		T2	2		T4	4
valid_sources[0x7e]	15149	1			T1	2		T2	2		T4	3
valid_sources[0x7f]	12793	1			T1	9		T2	10		T4	2
valid_sources[0x80]	12642	1			T1	2		T4	5		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331962

1

T1

109

T2

206

T3

1

values[0x0]

all_enables

biggest_size

143418

1

T1

79

T2

113

T3

3

values[0x1]

all_enables

biggest_size

129375

1

T1

86

T2

85

T3

1