SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_sideload_ctrl.u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[0].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[1].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[2].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[3].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[4].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[5].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[6].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[7].u_mubi_buf | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_sideload_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 7938 | 7938 | 0 | 0 |
OutputsKnown_A | 186126102 | 184667355 | 0 | 0 |
gen_no_flops.OutputDelay_A | 186126102 | 184667355 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7938 | 7938 | 0 | 0 |
T1 | 9 | 9 | 0 | 0 |
T2 | 9 | 9 | 0 | 0 |
T3 | 9 | 9 | 0 | 0 |
T4 | 9 | 9 | 0 | 0 |
T5 | 9 | 9 | 0 | 0 |
T6 | 9 | 9 | 0 | 0 |
T12 | 9 | 9 | 0 | 0 |
T13 | 9 | 9 | 0 | 0 |
T14 | 9 | 9 | 0 | 0 |
T15 | 9 | 9 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 186126102 | 184667355 | 0 | 0 |
T1 | 236961 | 236061 | 0 | 0 |
T2 | 25623 | 24732 | 0 | 0 |
T3 | 6714 | 6075 | 0 | 0 |
T4 | 67356 | 66627 | 0 | 0 |
T5 | 96111 | 94788 | 0 | 0 |
T6 | 67338 | 66546 | 0 | 0 |
T12 | 29043 | 28206 | 0 | 0 |
T13 | 128907 | 128160 | 0 | 0 |
T14 | 1197630 | 1191546 | 0 | 0 |
T15 | 38160 | 36909 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 186126102 | 184667355 | 0 | 0 |
T1 | 236961 | 236061 | 0 | 0 |
T2 | 25623 | 24732 | 0 | 0 |
T3 | 6714 | 6075 | 0 | 0 |
T4 | 67356 | 66627 | 0 | 0 |
T5 | 96111 | 94788 | 0 | 0 |
T6 | 67338 | 66546 | 0 | 0 |
T12 | 29043 | 28206 | 0 | 0 |
T13 | 128907 | 128160 | 0 | 0 |
T14 | 1197630 | 1191546 | 0 | 0 |
T15 | 38160 | 36909 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 882 | 882 | 0 | 0 |
OutputsKnown_A | 20680678 | 20518595 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20680678 | 20518595 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 882 | 882 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20680678 | 20518595 | 0 | 0 |
T1 | 26329 | 26229 | 0 | 0 |
T2 | 2847 | 2748 | 0 | 0 |
T3 | 746 | 675 | 0 | 0 |
T4 | 7484 | 7403 | 0 | 0 |
T5 | 10679 | 10532 | 0 | 0 |
T6 | 7482 | 7394 | 0 | 0 |
T12 | 3227 | 3134 | 0 | 0 |
T13 | 14323 | 14240 | 0 | 0 |
T14 | 133070 | 132394 | 0 | 0 |
T15 | 4240 | 4101 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |