Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
20680678 |
20518595 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20680678 |
20518595 |
0 |
0 |
T1 |
26329 |
26229 |
0 |
0 |
T2 |
2847 |
2748 |
0 |
0 |
T3 |
746 |
675 |
0 |
0 |
T4 |
7484 |
7403 |
0 |
0 |
T5 |
10679 |
10532 |
0 |
0 |
T6 |
7482 |
7394 |
0 |
0 |
T12 |
3227 |
3134 |
0 |
0 |
T13 |
14323 |
14240 |
0 |
0 |
T14 |
133070 |
132394 |
0 |
0 |
T15 |
4240 |
4101 |
0 |
0 |