Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22328620	20082	0	0
attest_sw_binding_0_rd_A	22328620	2321	0	0
attest_sw_binding_1_rd_A	22328620	2241	0	0
attest_sw_binding_2_rd_A	22328620	2216	0	0
attest_sw_binding_3_rd_A	22328620	2307	0	0
attest_sw_binding_4_rd_A	22328620	2395	0	0
attest_sw_binding_5_rd_A	22328620	2210	0	0
attest_sw_binding_6_rd_A	22328620	2251	0	0
attest_sw_binding_7_rd_A	22328620	2228	0	0
intr_enable_rd_A	22328620	2712	0	0
key_version_rd_A	22328620	2293	0	0
max_creator_key_ver_regwen_rd_A	22328620	2318	0	0
max_owner_int_key_ver_regwen_rd_A	22328620	2250	0	0
max_owner_key_ver_regwen_rd_A	22328620	2193	0	0
reseed_interval_regwen_rd_A	22328620	2298	0	0
salt_0_rd_A	22328620	2152	0	0
salt_1_rd_A	22328620	2113	0	0
salt_2_rd_A	22328620	2339	0	0
salt_3_rd_A	22328620	2365	0	0
salt_4_rd_A	22328620	2292	0	0
salt_5_rd_A	22328620	2383	0	0
salt_6_rd_A	22328620	2191	0	0
salt_7_rd_A	22328620	2319	0	0
sealing_sw_binding_0_rd_A	22328620	2250	0	0
sealing_sw_binding_1_rd_A	22328620	2272	0	0
sealing_sw_binding_2_rd_A	22328620	2233	0	0
sealing_sw_binding_3_rd_A	22328620	2314	0	0
sealing_sw_binding_4_rd_A	22328620	2334	0	0
sealing_sw_binding_5_rd_A	22328620	2286	0	0
sealing_sw_binding_6_rd_A	22328620	2326	0	0
sealing_sw_binding_7_rd_A	22328620	2273	0	0
sideload_clear_rd_A	22328620	2212	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	20082	0	0
T39	6881	0	0	0
T50	0	76	0	0
T55	2904	0	0	0
T61	43656	187	0	0
T67	24967	859	0	0
T68	37446	1301	0	0
T106	0	436	0	0
T114	0	382	0	0
T115	0	91	0	0
T116	0	268	0	0
T117	0	24	0	0
T118	20727	0	0	0
T119	7654	0	0	0
T120	2770	0	0	0
T121	3139	0	0	0
T122	10624	0	0	0
T125	0	44	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2321	0	0
T50	0	52	0	0
T65	35357	0	0	0
T115	62454	8	0	0
T125	0	35	0	0
T128	0	6	0	0
T148	0	22	0	0
T160	0	6	0	0
T161	0	55	0	0
T162	0	20	0	0
T163	0	4	0	0
T164	0	29	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2241	0	0
T50	0	87	0	0
T65	35357	0	0	0
T115	62454	13	0	0
T125	0	32	0	0
T128	0	13	0	0
T139	0	12	0	0
T148	0	31	0	0
T160	0	19	0	0
T161	0	56	0	0
T162	0	44	0	0
T164	0	33	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2216	0	0
T50	0	40	0	0
T65	35357	0	0	0
T115	62454	19	0	0
T125	0	6	0	0
T128	0	32	0	0
T148	0	36	0	0
T160	0	12	0	0
T161	0	62	0	0
T162	0	16	0	0
T164	0	28	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	3	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2307	0	0
T50	0	75	0	0
T65	35357	0	0	0
T115	62454	21	0	0
T125	0	31	0	0
T128	0	37	0	0
T148	0	44	0	0
T160	0	7	0	0
T161	0	36	0	0
T162	0	42	0	0
T164	0	34	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	6	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2395	0	0
T50	0	48	0	0
T65	35357	0	0	0
T115	62454	36	0	0
T125	0	61	0	0
T128	0	10	0	0
T148	0	46	0	0
T160	0	26	0	0
T161	0	56	0	0
T162	0	28	0	0
T164	0	29	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	9	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2210	0	0
T50	0	44	0	0
T65	35357	0	0	0
T115	62454	7	0	0
T125	0	23	0	0
T128	0	23	0	0
T148	0	32	0	0
T160	0	26	0	0
T161	0	66	0	0
T162	0	26	0	0
T164	0	37	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	1	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2251	0	0
T50	0	63	0	0
T65	35357	0	0	0
T115	62454	13	0	0
T125	0	21	0	0
T128	0	2	0	0
T148	0	52	0	0
T160	0	25	0	0
T161	0	59	0	0
T162	0	25	0	0
T164	0	32	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	5	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2228	0	0
T50	0	43	0	0
T65	35357	0	0	0
T115	62454	27	0	0
T125	0	26	0	0
T128	0	35	0	0
T148	0	27	0	0
T160	0	27	0	0
T161	0	39	0	0
T162	0	47	0	0
T164	0	19	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2712	0	0
T6	7482	0	0	0
T14	133070	12	0	0
T15	4240	0	0	0
T35	1959	0	0	0
T36	5555	0	0	0
T44	2732	0	0	0
T46	9604	0	0	0
T47	11576	0	0	0
T50	0	126	0	0
T72	0	46	0	0
T80	11264	0	0	0
T82	978	0	0	0
T115	0	39	0	0
T125	0	30	0	0
T148	0	23	0	0
T174	0	42	0	0
T175	0	5	0	0
T176	0	10	0	0
T177	0	20	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2293	0	0
T50	0	67	0	0
T65	35357	0	0	0
T115	62454	37	0	0
T125	0	26	0	0
T128	0	8	0	0
T148	0	43	0	0
T160	0	25	0	0
T161	0	37	0	0
T162	0	33	0	0
T164	0	29	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	15	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2318	0	0
T50	0	50	0	0
T65	35357	0	0	0
T115	62454	19	0	0
T125	0	31	0	0
T128	0	53	0	0
T139	0	14	0	0
T148	0	24	0	0
T160	0	26	0	0
T161	0	52	0	0
T162	0	33	0	0
T164	0	21	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2250	0	0
T50	0	63	0	0
T65	35357	0	0	0
T115	62454	51	0	0
T125	0	19	0	0
T128	0	25	0	0
T148	0	19	0	0
T160	0	28	0	0
T161	0	59	0	0
T162	0	42	0	0
T164	0	37	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	4	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2193	0	0
T50	0	66	0	0
T65	35357	0	0	0
T115	62454	29	0	0
T125	0	19	0	0
T128	0	29	0	0
T148	0	37	0	0
T160	0	25	0	0
T161	0	49	0	0
T162	0	27	0	0
T164	0	18	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	2	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2298	0	0
T50	0	51	0	0
T65	35357	0	0	0
T115	62454	23	0	0
T125	0	30	0	0
T128	0	27	0	0
T139	0	19	0	0
T148	0	28	0	0
T160	0	29	0	0
T161	0	52	0	0
T162	0	35	0	0
T164	0	35	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2152	0	0
T50	0	49	0	0
T65	35357	0	0	0
T115	62454	26	0	0
T125	0	20	0	0
T128	0	2	0	0
T148	0	17	0	0
T160	0	28	0	0
T161	0	62	0	0
T162	0	33	0	0
T164	0	34	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	8	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2113	0	0
T50	0	47	0	0
T65	35357	0	0	0
T115	62454	24	0	0
T125	0	25	0	0
T128	0	28	0	0
T148	0	17	0	0
T160	0	23	0	0
T161	0	59	0	0
T162	0	22	0	0
T164	0	30	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	1	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2339	0	0
T50	0	56	0	0
T65	35357	0	0	0
T115	62454	19	0	0
T125	0	30	0	0
T128	0	34	0	0
T148	0	42	0	0
T160	0	35	0	0
T161	0	55	0	0
T162	0	30	0	0
T164	0	31	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	2	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2365	0	0
T50	0	56	0	0
T65	35357	0	0	0
T115	62454	16	0	0
T125	0	24	0	0
T128	0	32	0	0
T148	0	32	0	0
T160	0	34	0	0
T161	0	50	0	0
T162	0	40	0	0
T164	0	24	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	1	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2292	0	0
T50	0	56	0	0
T65	35357	0	0	0
T115	62454	45	0	0
T125	0	23	0	0
T128	0	6	0	0
T148	0	33	0	0
T160	0	22	0	0
T161	0	71	0	0
T162	0	27	0	0
T164	0	49	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	2	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2383	0	0
T50	0	57	0	0
T65	35357	0	0	0
T115	62454	43	0	0
T125	0	20	0	0
T128	0	54	0	0
T148	0	30	0	0
T160	0	23	0	0
T161	0	60	0	0
T162	0	39	0	0
T164	0	40	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	11	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2191	0	0
T50	0	69	0	0
T65	35357	0	0	0
T115	62454	38	0	0
T125	0	37	0	0
T128	0	17	0	0
T148	0	25	0	0
T160	0	23	0	0
T161	0	77	0	0
T162	0	26	0	0
T164	0	24	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	15	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2319	0	0
T50	0	61	0	0
T65	35357	0	0	0
T115	62454	26	0	0
T125	0	25	0	0
T128	0	5	0	0
T148	0	22	0	0
T160	0	23	0	0
T161	0	61	0	0
T162	0	55	0	0
T164	0	37	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	6	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2250	0	0
T50	0	51	0	0
T65	35357	0	0	0
T115	62454	34	0	0
T125	0	22	0	0
T128	0	7	0	0
T148	0	42	0	0
T160	0	26	0	0
T161	0	32	0	0
T162	0	44	0	0
T164	0	25	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	7	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2272	0	0
T50	0	72	0	0
T65	35357	0	0	0
T115	62454	19	0	0
T125	0	18	0	0
T128	0	17	0	0
T139	0	18	0	0
T148	0	39	0	0
T160	0	33	0	0
T161	0	69	0	0
T162	0	10	0	0
T164	0	33	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2233	0	0
T50	0	46	0	0
T65	35357	0	0	0
T115	62454	25	0	0
T125	0	16	0	0
T128	0	46	0	0
T148	0	34	0	0
T160	0	41	0	0
T161	0	67	0	0
T162	0	30	0	0
T164	0	24	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	3	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2314	0	0
T50	0	80	0	0
T65	35357	0	0	0
T115	62454	26	0	0
T125	0	18	0	0
T128	0	30	0	0
T148	0	41	0	0
T160	0	11	0	0
T161	0	80	0	0
T162	0	16	0	0
T164	0	17	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	7	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2334	0	0
T50	0	76	0	0
T65	35357	0	0	0
T115	62454	19	0	0
T125	0	33	0	0
T128	0	37	0	0
T148	0	15	0	0
T160	0	27	0	0
T161	0	49	0	0
T162	0	44	0	0
T164	0	25	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T178	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2286	0	0
T50	0	58	0	0
T65	35357	0	0	0
T115	62454	40	0	0
T125	0	31	0	0
T128	0	2	0	0
T139	0	28	0	0
T148	0	25	0	0
T160	0	37	0	0
T161	0	66	0	0
T162	0	47	0	0
T164	0	21	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2326	0	0
T50	0	69	0	0
T65	35357	0	0	0
T115	62454	36	0	0
T125	0	24	0	0
T128	0	9	0	0
T148	0	35	0	0
T160	0	18	0	0
T161	0	36	0	0
T162	0	22	0	0
T164	0	16	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	13	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2273	0	0
T50	0	55	0	0
T65	35357	0	0	0
T115	62454	16	0	0
T125	0	33	0	0
T128	0	4	0	0
T148	0	35	0	0
T160	0	31	0	0
T161	0	31	0	0
T162	0	26	0	0
T164	0	40	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	8	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22328620	2212	0	0
T50	0	79	0	0
T65	35357	0	0	0
T115	62454	2	0	0
T125	0	31	0	0
T128	0	16	0	0
T148	0	61	0	0
T160	0	39	0	0
T161	0	53	0	0
T162	0	13	0	0
T164	0	17	0	0
T165	5036	0	0	0
T166	24060	0	0	0
T167	61007	0	0	0
T168	127029	0	0	0
T169	34761	0	0	0
T170	1811	0	0	0
T171	3766	0	0	0
T172	8613	0	0	0
T173	0	2	0	0