Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4180884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

649238

1

T1

303

T2

449

T3

150

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4381869	1			T1	10337		T2	1591		T3	452
values[0x0]	222518	1			T1	122		T2	197		T3	42
values[0x1]	225735	1			T1	117		T2	220		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2849029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1981093

1

T1

3689

T2

936

T3

239

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20112	1			T1	42		T2	7		T4	3
valid_sources[0x01]	14070	1			T1	35		T2	5		T3	41
valid_sources[0x02]	14444	1			T1	41		T2	7		T4	1
valid_sources[0x03]	26209	1			T1	49		T2	6		T4	2
valid_sources[0x04]	15081	1			T1	42		T2	13		T4	4
valid_sources[0x05]	15914	1			T1	52		T2	13		T3	38
valid_sources[0x06]	17637	1			T1	59		T2	8		T4	4
valid_sources[0x07]	16558	1			T1	51		T2	8		T4	1
valid_sources[0x08]	25087	1			T1	48		T2	6		T4	2
valid_sources[0x09]	15559	1			T1	48		T2	11		T4	3
valid_sources[0x0a]	14714	1			T1	34		T2	9		T4	4
valid_sources[0x0b]	15284	1			T1	55		T2	17		T16	2
valid_sources[0x0c]	15680	1			T1	45		T2	6		T4	3
valid_sources[0x0d]	16801	1			T1	40		T2	8		T4	3
valid_sources[0x0e]	13970	1			T1	53		T2	8		T4	7
valid_sources[0x0f]	14322	1			T1	36		T2	3		T4	2
valid_sources[0x10]	14169	1			T1	41		T2	8		T4	1
valid_sources[0x11]	14911	1			T1	49		T2	3		T4	1
valid_sources[0x12]	14906	1			T1	40		T2	5		T4	1
valid_sources[0x13]	15301	1			T1	44		T2	4		T4	2
valid_sources[0x14]	16577	1			T1	41		T2	13		T4	1
valid_sources[0x15]	15051	1			T1	41		T2	7		T4	2
valid_sources[0x16]	20845	1			T1	48		T2	2		T4	3
valid_sources[0x17]	14123	1			T1	34		T2	10		T4	1
valid_sources[0x18]	17190	1			T1	33		T2	6		T4	4
valid_sources[0x19]	41981	1			T1	31		T2	6		T3	13
valid_sources[0x1a]	14141	1			T1	35		T2	6		T4	2
valid_sources[0x1b]	14093	1			T1	30		T2	4		T4	2
valid_sources[0x1c]	16087	1			T1	47		T2	7		T4	4
valid_sources[0x1d]	16422	1			T1	44		T2	7		T4	2
valid_sources[0x1e]	18458	1			T1	43		T2	5		T4	2
valid_sources[0x1f]	14013	1			T1	48		T2	10		T4	2
valid_sources[0x20]	46403	1			T1	45		T2	6		T4	3
valid_sources[0x21]	30524	1			T1	46		T2	5		T4	5
valid_sources[0x22]	19586	1			T1	53		T2	7		T4	2
valid_sources[0x23]	13705	1			T1	34		T2	5		T3	7
valid_sources[0x24]	43549	1			T1	42		T2	2		T17	5
valid_sources[0x25]	13904	1			T1	54		T2	11		T3	11
valid_sources[0x26]	14260	1			T1	32		T2	11		T3	2
valid_sources[0x27]	14590	1			T1	41		T2	8		T4	3
valid_sources[0x28]	14098	1			T1	45		T2	3		T4	6
valid_sources[0x29]	15308	1			T1	34		T2	8		T4	2
valid_sources[0x2a]	15171	1			T1	54		T2	11		T4	3
valid_sources[0x2b]	14045	1			T1	40		T2	9		T3	19
valid_sources[0x2c]	14640	1			T1	45		T2	6		T4	2
valid_sources[0x2d]	14768	1			T1	27		T2	14		T4	3
valid_sources[0x2e]	14304	1			T1	37		T2	14		T4	2
valid_sources[0x2f]	14973	1			T1	49		T2	8		T4	4
valid_sources[0x30]	27077	1			T1	39		T2	4		T4	2
valid_sources[0x31]	15915	1			T1	26		T2	3		T3	6
valid_sources[0x32]	13948	1			T1	49		T2	10		T16	1
valid_sources[0x33]	14985	1			T1	40		T2	4		T4	4
valid_sources[0x34]	110596	1			T1	36		T2	6		T16	5
valid_sources[0x35]	16204	1			T1	33		T2	9		T4	1
valid_sources[0x36]	14027	1			T1	37		T2	8		T4	2
valid_sources[0x37]	15189	1			T1	57		T2	13		T4	1
valid_sources[0x38]	14557	1			T1	50		T2	9		T4	2
valid_sources[0x39]	15040	1			T1	41		T2	10		T4	4
valid_sources[0x3a]	15992	1			T1	31		T2	9		T4	4
valid_sources[0x3b]	22965	1			T1	49		T2	12		T16	8
valid_sources[0x3c]	21806	1			T1	56		T2	3		T4	1
valid_sources[0x3d]	15265	1			T1	34		T4	3		T16	6
valid_sources[0x3e]	15539	1			T1	49		T2	8		T17	2
valid_sources[0x3f]	14799	1			T1	50		T2	8		T4	2
valid_sources[0x40]	14130	1			T1	28		T2	9		T4	1
valid_sources[0x41]	16473	1			T1	40		T2	8		T4	3
valid_sources[0x42]	15023	1			T1	39		T2	7		T3	31
valid_sources[0x43]	16334	1			T1	48		T2	11		T16	3
valid_sources[0x44]	14064	1			T1	50		T2	3		T4	2
valid_sources[0x45]	15009	1			T1	40		T2	6		T4	2
valid_sources[0x46]	15014	1			T1	41		T2	8		T4	2
valid_sources[0x47]	15007	1			T1	33		T2	13		T4	5
valid_sources[0x48]	14862	1			T1	35		T2	10		T4	3
valid_sources[0x49]	14598	1			T1	42		T2	8		T4	6
valid_sources[0x4a]	29786	1			T1	36		T2	13		T4	2
valid_sources[0x4b]	15396	1			T1	46		T2	9		T16	2
valid_sources[0x4c]	20268	1			T1	36		T2	14		T4	2
valid_sources[0x4d]	14128	1			T1	37		T2	4		T4	1
valid_sources[0x4e]	15808	1			T1	46		T2	10		T4	2
valid_sources[0x4f]	14735	1			T1	31		T2	15		T4	2
valid_sources[0x50]	31734	1			T1	58		T2	8		T4	1
valid_sources[0x51]	23732	1			T1	46		T2	13		T16	1
valid_sources[0x52]	14188	1			T1	51		T2	10		T4	1
valid_sources[0x53]	16919	1			T1	41		T2	6		T4	2
valid_sources[0x54]	14007	1			T1	36		T2	12		T4	2
valid_sources[0x55]	15092	1			T1	56		T2	8		T17	1
valid_sources[0x56]	16856	1			T1	33		T2	10		T4	3
valid_sources[0x57]	15216	1			T1	53		T2	10		T4	2
valid_sources[0x58]	15425	1			T1	45		T2	2		T4	3
valid_sources[0x59]	14084	1			T1	23		T2	12		T3	15
valid_sources[0x5a]	14592	1			T1	46		T2	8		T3	13
valid_sources[0x5b]	14311	1			T1	37		T2	14		T4	1
valid_sources[0x5c]	14631	1			T1	32		T2	8		T4	2
valid_sources[0x5d]	14675	1			T1	48		T2	8		T4	2
valid_sources[0x5e]	14956	1			T1	33		T2	10		T4	3
valid_sources[0x5f]	20381	1			T1	51		T2	6		T3	73
valid_sources[0x60]	14080	1			T1	19		T2	6		T16	1
valid_sources[0x61]	14709	1			T1	39		T2	4		T4	1
valid_sources[0x62]	21161	1			T1	24		T2	10		T4	2
valid_sources[0x63]	16422	1			T1	39		T2	4		T16	1
valid_sources[0x64]	15310	1			T1	49		T2	6		T4	3
valid_sources[0x65]	15537	1			T1	39		T2	5		T4	1
valid_sources[0x66]	15738	1			T1	32		T2	16		T3	33
valid_sources[0x67]	28278	1			T1	39		T2	11		T17	1
valid_sources[0x68]	14861	1			T1	50		T2	4		T4	2
valid_sources[0x69]	31664	1			T1	30		T2	9		T4	1
valid_sources[0x6a]	22481	1			T1	42		T2	6		T4	4
valid_sources[0x6b]	16250	1			T1	36		T2	4		T4	1
valid_sources[0x6c]	15315	1			T1	29		T2	2		T4	2
valid_sources[0x6d]	15141	1			T1	48		T2	9		T17	2
valid_sources[0x6e]	14436	1			T1	45		T2	7		T4	3
valid_sources[0x6f]	20887	1			T1	66		T2	15		T4	4
valid_sources[0x70]	17141	1			T1	39		T2	7		T4	1
valid_sources[0x71]	14087	1			T1	21		T2	12		T4	4
valid_sources[0x72]	13743	1			T1	50		T2	6		T16	4
valid_sources[0x73]	17682	1			T1	48		T2	9		T4	7
valid_sources[0x74]	25773	1			T1	30		T2	7		T4	3
valid_sources[0x75]	13627	1			T1	44		T2	12		T4	1
valid_sources[0x76]	18318	1			T1	43		T2	4		T4	2
valid_sources[0x77]	16036	1			T1	38		T2	7		T16	5
valid_sources[0x78]	15954	1			T1	47		T2	16		T4	4
valid_sources[0x79]	14259	1			T1	48		T2	8		T4	3
valid_sources[0x7a]	14787	1			T1	27		T2	15		T4	3
valid_sources[0x7b]	57557	1			T1	42		T2	14		T4	1
valid_sources[0x7c]	15226	1			T1	24		T2	5		T3	8
valid_sources[0x7d]	15328	1			T1	32		T2	10		T16	4
valid_sources[0x7e]	14429	1			T1	35		T2	4		T4	5
valid_sources[0x7f]	23282	1			T1	37		T2	4		T4	1
valid_sources[0x80]	14690	1			T1	34		T2	2		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

344162

1

T1

127

T2

176

T3

119

values[0x0]

all_enables

biggest_size

160241

1

T1

94

T2

141

T3

18

values[0x1]

all_enables

biggest_size

144835

1

T1

82

T2

132

T3

13