SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_sideload_ctrl.u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[0].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[1].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[2].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[3].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[4].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[5].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[6].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[7].u_mubi_buf | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_sideload_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.05 | 96.00 | 98.36 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 7929 | 7929 | 0 | 0 |
OutputsKnown_A | 237012696 | 235426986 | 0 | 0 |
gen_no_flops.OutputDelay_A | 237012696 | 235426986 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7929 | 7929 | 0 | 0 |
T1 | 9 | 9 | 0 | 0 |
T2 | 9 | 9 | 0 | 0 |
T3 | 9 | 9 | 0 | 0 |
T4 | 9 | 9 | 0 | 0 |
T14 | 9 | 9 | 0 | 0 |
T15 | 9 | 9 | 0 | 0 |
T16 | 9 | 9 | 0 | 0 |
T17 | 9 | 9 | 0 | 0 |
T18 | 9 | 9 | 0 | 0 |
T19 | 9 | 9 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 237012696 | 235426986 | 0 | 0 |
T1 | 539253 | 538587 | 0 | 0 |
T2 | 61479 | 61002 | 0 | 0 |
T3 | 44469 | 43641 | 0 | 0 |
T4 | 18684 | 18018 | 0 | 0 |
T14 | 442323 | 441648 | 0 | 0 |
T15 | 30636 | 29385 | 0 | 0 |
T16 | 81549 | 80802 | 0 | 0 |
T17 | 65034 | 64224 | 0 | 0 |
T18 | 70668 | 70137 | 0 | 0 |
T19 | 63774 | 63162 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 237012696 | 235426986 | 0 | 0 |
T1 | 539253 | 538587 | 0 | 0 |
T2 | 61479 | 61002 | 0 | 0 |
T3 | 44469 | 43641 | 0 | 0 |
T4 | 18684 | 18018 | 0 | 0 |
T14 | 442323 | 441648 | 0 | 0 |
T15 | 30636 | 29385 | 0 | 0 |
T16 | 81549 | 80802 | 0 | 0 |
T17 | 65034 | 64224 | 0 | 0 |
T18 | 70668 | 70137 | 0 | 0 |
T19 | 63774 | 63162 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 881 | 881 | 0 | 0 |
OutputsKnown_A | 26334744 | 26158554 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26334744 | 26158554 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 881 | 881 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26334744 | 26158554 | 0 | 0 |
T1 | 59917 | 59843 | 0 | 0 |
T2 | 6831 | 6778 | 0 | 0 |
T3 | 4941 | 4849 | 0 | 0 |
T4 | 2076 | 2002 | 0 | 0 |
T14 | 49147 | 49072 | 0 | 0 |
T15 | 3404 | 3265 | 0 | 0 |
T16 | 9061 | 8978 | 0 | 0 |
T17 | 7226 | 7136 | 0 | 0 |
T18 | 7852 | 7793 | 0 | 0 |
T19 | 7086 | 7018 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |