Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
26334744 |
26158554 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26334744 |
26158554 |
0 |
0 |
T1 |
59917 |
59843 |
0 |
0 |
T2 |
6831 |
6778 |
0 |
0 |
T3 |
4941 |
4849 |
0 |
0 |
T4 |
2076 |
2002 |
0 |
0 |
T14 |
49147 |
49072 |
0 |
0 |
T15 |
3404 |
3265 |
0 |
0 |
T16 |
9061 |
8978 |
0 |
0 |
T17 |
7226 |
7136 |
0 |
0 |
T18 |
7852 |
7793 |
0 |
0 |
T19 |
7086 |
7018 |
0 |
0 |