Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3278164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

660516

1

T1

2345

T2

156

T3

258

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3515204	1			T1	6026		T2	256		T3	221
values[0x0]	210181	1			T1	679		T2	50		T3	111
values[0x1]	213295	1			T1	641		T2	49		T3	141

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2251131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1687549

1

T1

3604

T2

211

T3

297

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15281	1			T1	32		T3	3		T5	15
valid_sources[0x01]	22624	1			T1	19		T4	3		T5	23
valid_sources[0x02]	26368	1			T1	29		T3	1		T4	1
valid_sources[0x03]	11374	1			T1	29		T3	4		T4	4
valid_sources[0x04]	11578	1			T1	23		T3	1		T4	2
valid_sources[0x05]	43021	1			T1	35		T3	3		T4	8
valid_sources[0x06]	11962	1			T1	30		T2	4		T3	1
valid_sources[0x07]	12439	1			T1	22		T4	1		T5	35
valid_sources[0x08]	11382	1			T1	20		T3	2		T4	1
valid_sources[0x09]	11760	1			T1	13		T2	1		T3	1
valid_sources[0x0a]	11829	1			T1	18		T2	2		T3	3
valid_sources[0x0b]	15290	1			T1	37		T3	2		T5	26
valid_sources[0x0c]	11047	1			T1	31		T2	3		T3	3
valid_sources[0x0d]	12547	1			T1	28		T3	3		T5	30
valid_sources[0x0e]	12499	1			T1	29		T3	1		T5	35
valid_sources[0x0f]	11346	1			T1	25		T2	1		T3	4
valid_sources[0x10]	14117	1			T1	21		T2	4		T3	1
valid_sources[0x11]	13570	1			T1	40		T3	3		T4	3
valid_sources[0x12]	14269	1			T1	25		T3	2		T5	28
valid_sources[0x13]	12198	1			T1	31		T2	21		T4	4
valid_sources[0x14]	19880	1			T1	32		T3	5		T4	6
valid_sources[0x15]	11750	1			T1	30		T3	1		T4	1
valid_sources[0x16]	17424	1			T1	33		T4	1		T5	26
valid_sources[0x17]	25236	1			T1	12		T2	6		T3	2
valid_sources[0x18]	11296	1			T1	42		T2	14		T3	2
valid_sources[0x19]	11371	1			T1	15		T2	5		T4	1
valid_sources[0x1a]	14419	1			T1	18		T3	3		T4	2
valid_sources[0x1b]	32833	1			T1	37		T2	1		T3	1
valid_sources[0x1c]	12563	1			T1	27		T4	3		T5	19
valid_sources[0x1d]	12485	1			T1	30		T2	1		T3	4
valid_sources[0x1e]	11967	1			T1	17		T2	2		T3	6
valid_sources[0x1f]	19516	1			T1	24		T3	5		T5	22
valid_sources[0x20]	13601	1			T1	39		T3	2		T4	7
valid_sources[0x21]	13707	1			T1	16		T3	1		T4	4
valid_sources[0x22]	18204	1			T1	22		T3	1		T4	2
valid_sources[0x23]	13319	1			T1	27		T2	1		T4	4
valid_sources[0x24]	13740	1			T1	25		T3	3		T4	1
valid_sources[0x25]	13860	1			T1	34		T3	2		T4	2
valid_sources[0x26]	14578	1			T1	15		T2	7		T3	2
valid_sources[0x27]	13142	1			T1	38		T4	2		T5	27
valid_sources[0x28]	12676	1			T1	24		T3	3		T4	1
valid_sources[0x29]	12030	1			T1	31		T2	2		T3	4
valid_sources[0x2a]	14072	1			T1	38		T3	5		T5	28
valid_sources[0x2b]	12684	1			T1	30		T3	1		T4	1
valid_sources[0x2c]	11900	1			T1	30		T3	1		T4	2
valid_sources[0x2d]	12062	1			T1	25		T3	3		T4	1
valid_sources[0x2e]	15360	1			T1	26		T3	2		T4	4
valid_sources[0x2f]	12771	1			T1	29		T3	2		T4	3
valid_sources[0x30]	11827	1			T1	35		T3	1		T4	1
valid_sources[0x31]	11570	1			T1	22		T2	6		T3	2
valid_sources[0x32]	12817	1			T1	18		T3	4		T4	4
valid_sources[0x33]	14590	1			T1	28		T2	2		T3	1
valid_sources[0x34]	11645	1			T1	32		T4	2		T5	21
valid_sources[0x35]	15955	1			T1	21		T2	4		T4	2
valid_sources[0x36]	11345	1			T1	27		T3	1		T5	34
valid_sources[0x37]	11357	1			T1	24		T3	3		T4	2
valid_sources[0x38]	15915	1			T1	24		T3	1		T5	29
valid_sources[0x39]	11707	1			T1	42		T2	1		T3	1
valid_sources[0x3a]	11437	1			T1	19		T4	1		T5	22
valid_sources[0x3b]	12920	1			T1	33		T2	2		T4	4
valid_sources[0x3c]	12083	1			T1	39		T2	1		T3	1
valid_sources[0x3d]	13262	1			T1	22		T3	2		T4	1
valid_sources[0x3e]	12381	1			T1	27		T5	25		T14	5
valid_sources[0x3f]	61341	1			T1	30		T3	2		T4	3
valid_sources[0x40]	12120	1			T1	15		T2	3		T3	3
valid_sources[0x41]	11105	1			T1	21		T3	1		T5	27
valid_sources[0x42]	13901	1			T1	17		T3	1		T4	3
valid_sources[0x43]	13806	1			T1	40		T3	3		T4	2
valid_sources[0x44]	14806	1			T1	33		T4	2		T5	24
valid_sources[0x45]	13288	1			T1	24		T3	1		T4	4
valid_sources[0x46]	18756	1			T1	29		T4	2		T5	31
valid_sources[0x47]	15339	1			T1	25		T3	2		T5	33
valid_sources[0x48]	20326	1			T1	21		T2	1		T4	3
valid_sources[0x49]	12332	1			T1	28		T2	2		T3	2
valid_sources[0x4a]	18934	1			T1	26		T3	2		T4	2
valid_sources[0x4b]	70477	1			T1	34		T2	1		T3	1
valid_sources[0x4c]	11992	1			T1	30		T2	1		T4	1
valid_sources[0x4d]	20379	1			T1	22		T2	5		T3	1
valid_sources[0x4e]	12209	1			T1	19		T4	1		T5	31
valid_sources[0x4f]	17882	1			T1	21		T3	2		T4	6
valid_sources[0x50]	12256	1			T1	40		T4	2		T5	37
valid_sources[0x51]	11799	1			T1	18		T2	7		T4	2
valid_sources[0x52]	12387	1			T1	25		T3	1		T4	3
valid_sources[0x53]	12019	1			T1	38		T3	5		T4	1
valid_sources[0x54]	11040	1			T1	24		T4	3		T5	25
valid_sources[0x55]	13714	1			T1	27		T3	4		T4	1
valid_sources[0x56]	28065	1			T1	40		T3	2		T5	22
valid_sources[0x57]	13243	1			T1	15		T3	5		T4	6
valid_sources[0x58]	21916	1			T1	25		T2	3		T4	1
valid_sources[0x59]	13061	1			T1	34		T2	6		T3	4
valid_sources[0x5a]	11989	1			T1	31		T2	1		T3	3
valid_sources[0x5b]	12659	1			T1	25		T2	7		T3	2
valid_sources[0x5c]	11470	1			T1	37		T3	1		T4	1
valid_sources[0x5d]	11742	1			T1	51		T3	3		T4	1
valid_sources[0x5e]	11245	1			T1	18		T3	1		T4	1
valid_sources[0x5f]	16511	1			T1	21		T2	2		T3	2
valid_sources[0x60]	11321	1			T1	30		T3	1		T4	4
valid_sources[0x61]	10840	1			T1	23		T3	4		T4	3
valid_sources[0x62]	13941	1			T1	30		T2	14		T3	6
valid_sources[0x63]	15634	1			T1	28		T2	1		T3	1
valid_sources[0x64]	12540	1			T1	40		T2	1		T3	1
valid_sources[0x65]	11587	1			T1	32		T2	2		T4	3
valid_sources[0x66]	21109	1			T1	20		T3	2		T4	1
valid_sources[0x67]	13363	1			T1	35		T2	3		T3	7
valid_sources[0x68]	16712	1			T1	29		T2	4		T3	1
valid_sources[0x69]	12757	1			T1	24		T3	1		T4	7
valid_sources[0x6a]	13428	1			T1	32		T3	1		T4	6
valid_sources[0x6b]	12570	1			T1	26		T2	6		T3	1
valid_sources[0x6c]	12593	1			T1	32		T4	9		T5	37
valid_sources[0x6d]	12640	1			T1	31		T2	2		T3	2
valid_sources[0x6e]	12425	1			T1	27		T2	3		T3	1
valid_sources[0x6f]	13514	1			T1	37		T2	1		T3	4
valid_sources[0x70]	13513	1			T1	27		T5	28		T14	4
valid_sources[0x71]	19285	1			T1	37		T2	1		T3	1
valid_sources[0x72]	12447	1			T1	25		T3	1		T4	6
valid_sources[0x73]	13738	1			T1	17		T3	3		T4	1
valid_sources[0x74]	11391	1			T1	45		T2	1		T3	1
valid_sources[0x75]	12795	1			T1	36		T3	3		T4	4
valid_sources[0x76]	11414	1			T1	39		T3	1		T4	1
valid_sources[0x77]	14608	1			T1	33		T2	6		T4	3
valid_sources[0x78]	12365	1			T1	16		T3	2		T5	20
valid_sources[0x79]	12119	1			T1	22		T2	6		T3	1
valid_sources[0x7a]	12953	1			T1	22		T2	3		T3	2
valid_sources[0x7b]	13630	1			T1	45		T2	9		T3	2
valid_sources[0x7c]	13517	1			T1	30		T2	5		T3	1
valid_sources[0x7d]	13885	1			T1	26		T3	2		T5	31
valid_sources[0x7e]	11516	1			T1	39		T2	2		T3	3
valid_sources[0x7f]	12903	1			T1	27		T3	1		T4	2
valid_sources[0x80]	12367	1			T1	43		T3	3		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

372941

1

T1

1769

T2

108

T3

97

values[0x0]

all_enables

biggest_size

151072

1

T1

340

T2

27

T3

72

values[0x1]

all_enables

biggest_size

136503

1

T1

236

T2

21

T3

89