Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 26690436 16525 0 0
attest_sw_binding_0_rd_A 26690436 3215 0 0
attest_sw_binding_1_rd_A 26690436 3155 0 0
attest_sw_binding_2_rd_A 26690436 3303 0 0
attest_sw_binding_3_rd_A 26690436 3260 0 0
attest_sw_binding_4_rd_A 26690436 3128 0 0
attest_sw_binding_5_rd_A 26690436 3091 0 0
attest_sw_binding_6_rd_A 26690436 3333 0 0
attest_sw_binding_7_rd_A 26690436 3145 0 0
intr_enable_rd_A 26690436 3897 0 0
key_version_rd_A 26690436 3208 0 0
max_creator_key_ver_regwen_rd_A 26690436 3263 0 0
max_owner_int_key_ver_regwen_rd_A 26690436 3118 0 0
max_owner_key_ver_regwen_rd_A 26690436 3240 0 0
reseed_interval_regwen_rd_A 26690436 3364 0 0
salt_0_rd_A 26690436 3353 0 0
salt_1_rd_A 26690436 3356 0 0
salt_2_rd_A 26690436 3186 0 0
salt_3_rd_A 26690436 3413 0 0
salt_4_rd_A 26690436 3209 0 0
salt_5_rd_A 26690436 3095 0 0
salt_6_rd_A 26690436 3360 0 0
salt_7_rd_A 26690436 3194 0 0
sealing_sw_binding_0_rd_A 26690436 3196 0 0
sealing_sw_binding_1_rd_A 26690436 3295 0 0
sealing_sw_binding_2_rd_A 26690436 3199 0 0
sealing_sw_binding_3_rd_A 26690436 3288 0 0
sealing_sw_binding_4_rd_A 26690436 3198 0 0
sealing_sw_binding_5_rd_A 26690436 3245 0 0
sealing_sw_binding_6_rd_A 26690436 3084 0 0
sealing_sw_binding_7_rd_A 26690436 3212 0 0
sideload_clear_rd_A 26690436 3258 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 16525 0 0
T15 30197 163 0 0
T16 24683 0 0 0
T17 19357 0 0 0
T18 16519 543 0 0
T34 5160 0 0 0
T35 5998 0 0 0
T36 8527 0 0 0
T37 3366 0 0 0
T49 12450 236 0 0
T61 0 28 0 0
T83 17220 0 0 0
T119 0 346 0 0
T120 0 283 0 0
T121 0 136 0 0
T122 0 58 0 0
T123 0 62 0 0
T124 0 1104 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3215 0 0
T25 10516 0 0 0
T52 0 24 0 0
T61 20116 29 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 45 0 0
T120 14363 0 0 0
T122 0 6 0 0
T127 22125 0 0 0
T171 0 70 0 0
T172 0 31 0 0
T173 0 26 0 0
T174 0 27 0 0
T175 0 18 0 0
T176 0 8 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3155 0 0
T52 0 24 0 0
T66 79638 0 0 0
T75 0 57 0 0
T88 2648 0 0 0
T115 0 76 0 0
T122 31153 19 0 0
T141 2710 0 0 0
T171 0 85 0 0
T172 0 18 0 0
T173 0 29 0 0
T174 0 36 0 0
T175 0 6 0 0
T176 0 11 0 0
T181 8199 0 0 0
T182 2639 0 0 0
T183 13769 0 0 0
T184 3163 0 0 0
T185 2825 0 0 0
T186 3199 0 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3303 0 0
T25 10516 0 0 0
T52 0 13 0 0
T61 20116 13 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 90 0 0
T120 14363 0 0 0
T122 0 9 0 0
T127 22125 0 0 0
T171 0 58 0 0
T172 0 22 0 0
T173 0 33 0 0
T174 0 39 0 0
T175 0 29 0 0
T176 0 12 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3260 0 0
T25 10516 0 0 0
T52 0 16 0 0
T61 20116 17 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 82 0 0
T120 14363 0 0 0
T122 0 15 0 0
T127 22125 0 0 0
T171 0 73 0 0
T172 0 23 0 0
T173 0 17 0 0
T174 0 10 0 0
T175 0 15 0 0
T176 0 5 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3128 0 0
T25 10516 0 0 0
T52 0 27 0 0
T61 20116 2 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 91 0 0
T120 14363 0 0 0
T122 0 20 0 0
T127 22125 0 0 0
T171 0 62 0 0
T172 0 10 0 0
T173 0 35 0 0
T174 0 20 0 0
T175 0 17 0 0
T176 0 6 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3091 0 0
T25 10516 0 0 0
T52 0 48 0 0
T61 20116 19 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 59 0 0
T115 0 70 0 0
T120 14363 0 0 0
T122 0 21 0 0
T127 22125 0 0 0
T171 0 79 0 0
T172 0 30 0 0
T173 0 24 0 0
T174 0 30 0 0
T175 0 12 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3333 0 0
T25 10516 0 0 0
T43 0 1 0 0
T52 0 14 0 0
T61 20116 9 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 70 0 0
T120 14363 0 0 0
T122 0 17 0 0
T127 22125 0 0 0
T171 0 90 0 0
T172 0 15 0 0
T173 0 39 0 0
T174 0 30 0 0
T175 0 27 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3145 0 0
T25 10516 0 0 0
T52 0 15 0 0
T61 20116 20 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 52 0 0
T120 14363 0 0 0
T122 0 7 0 0
T127 22125 0 0 0
T171 0 64 0 0
T172 0 24 0 0
T173 0 35 0 0
T174 0 28 0 0
T175 0 20 0 0
T176 0 10 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3897 0 0
T6 460346 40 0 0
T7 48397 0 0 0
T46 925603 62 0 0
T55 8897 0 0 0
T60 2935 0 0 0
T61 0 17 0 0
T64 0 23 0 0
T75 0 98 0 0
T122 0 15 0 0
T125 5931 0 0 0
T171 0 131 0 0
T172 0 14 0 0
T187 0 55 0 0
T188 0 15 0 0
T189 7607 0 0 0
T190 4585 0 0 0
T191 5357 0 0 0
T192 11561 0 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3208 0 0
T25 10516 0 0 0
T52 0 31 0 0
T61 20116 18 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 61 0 0
T120 14363 0 0 0
T122 0 17 0 0
T127 22125 0 0 0
T171 0 51 0 0
T172 0 15 0 0
T173 0 38 0 0
T174 0 23 0 0
T175 0 29 0 0
T176 0 9 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3263 0 0
T25 10516 0 0 0
T52 0 38 0 0
T61 20116 16 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 60 0 0
T115 0 61 0 0
T120 14363 0 0 0
T122 0 12 0 0
T127 22125 0 0 0
T171 0 58 0 0
T172 0 18 0 0
T173 0 24 0 0
T174 0 40 0 0
T175 0 6 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3118 0 0
T25 10516 0 0 0
T52 0 37 0 0
T61 20116 13 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 57 0 0
T120 14363 0 0 0
T122 0 1 0 0
T127 22125 0 0 0
T171 0 38 0 0
T172 0 11 0 0
T173 0 17 0 0
T174 0 27 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0
T193 0 1 0 0
T194 0 1 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3240 0 0
T25 10516 0 0 0
T52 0 41 0 0
T61 20116 11 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 42 0 0
T120 14363 0 0 0
T122 0 21 0 0
T127 22125 0 0 0
T171 0 47 0 0
T172 0 34 0 0
T173 0 20 0 0
T174 0 25 0 0
T175 0 21 0 0
T176 0 5 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3364 0 0
T25 10516 0 0 0
T52 0 29 0 0
T61 20116 8 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 52 0 0
T120 14363 0 0 0
T122 0 26 0 0
T127 22125 0 0 0
T171 0 71 0 0
T172 0 16 0 0
T173 0 53 0 0
T174 0 24 0 0
T175 0 27 0 0
T176 0 10 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3353 0 0
T25 10516 0 0 0
T52 0 37 0 0
T61 20116 4 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 87 0 0
T115 0 84 0 0
T120 14363 0 0 0
T122 0 7 0 0
T127 22125 0 0 0
T171 0 103 0 0
T172 0 10 0 0
T173 0 22 0 0
T174 0 39 0 0
T175 0 26 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3356 0 0
T25 10516 0 0 0
T52 0 22 0 0
T61 20116 8 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 59 0 0
T115 0 82 0 0
T120 14363 0 0 0
T122 0 33 0 0
T127 22125 0 0 0
T171 0 86 0 0
T172 0 1 0 0
T173 0 42 0 0
T174 0 39 0 0
T175 0 13 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3186 0 0
T25 10516 0 0 0
T52 0 27 0 0
T61 20116 25 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 81 0 0
T120 14363 0 0 0
T122 0 12 0 0
T127 22125 0 0 0
T171 0 63 0 0
T172 0 24 0 0
T173 0 27 0 0
T174 0 39 0 0
T175 0 8 0 0
T176 0 4 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3413 0 0
T25 10516 0 0 0
T52 0 24 0 0
T61 20116 22 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 88 0 0
T120 14363 0 0 0
T122 0 21 0 0
T127 22125 0 0 0
T171 0 100 0 0
T172 0 16 0 0
T173 0 25 0 0
T174 0 21 0 0
T175 0 23 0 0
T176 0 17 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3209 0 0
T25 10516 0 0 0
T52 0 18 0 0
T61 20116 7 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 72 0 0
T120 14363 0 0 0
T122 0 13 0 0
T127 22125 0 0 0
T171 0 68 0 0
T172 0 9 0 0
T173 0 30 0 0
T174 0 23 0 0
T175 0 19 0 0
T176 0 2 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3095 0 0
T25 10516 0 0 0
T52 0 13 0 0
T61 20116 8 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 54 0 0
T120 14363 0 0 0
T122 0 9 0 0
T127 22125 0 0 0
T171 0 68 0 0
T172 0 2 0 0
T173 0 20 0 0
T174 0 36 0 0
T175 0 11 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0
T195 0 7 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3360 0 0
T25 10516 0 0 0
T52 0 52 0 0
T61 20116 4 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 87 0 0
T120 14363 0 0 0
T122 0 12 0 0
T127 22125 0 0 0
T171 0 53 0 0
T172 0 9 0 0
T173 0 13 0 0
T174 0 23 0 0
T175 0 34 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0
T196 0 5 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3194 0 0
T25 10516 0 0 0
T52 0 25 0 0
T61 20116 16 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 70 0 0
T120 14363 0 0 0
T122 0 31 0 0
T127 22125 0 0 0
T171 0 71 0 0
T172 0 30 0 0
T173 0 47 0 0
T174 0 26 0 0
T175 0 22 0 0
T176 0 22 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3196 0 0
T25 10516 0 0 0
T52 0 26 0 0
T61 20116 14 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 74 0 0
T120 14363 0 0 0
T122 0 17 0 0
T127 22125 0 0 0
T171 0 66 0 0
T172 0 13 0 0
T173 0 26 0 0
T174 0 33 0 0
T175 0 10 0 0
T176 0 7 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3295 0 0
T25 10516 0 0 0
T52 0 36 0 0
T61 20116 4 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 86 0 0
T120 14363 0 0 0
T122 0 4 0 0
T127 22125 0 0 0
T171 0 81 0 0
T172 0 19 0 0
T173 0 44 0 0
T174 0 25 0 0
T175 0 39 0 0
T176 0 16 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3199 0 0
T25 10516 0 0 0
T52 0 22 0 0
T61 20116 24 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 50 0 0
T120 14363 0 0 0
T122 0 31 0 0
T127 22125 0 0 0
T171 0 86 0 0
T172 0 16 0 0
T173 0 21 0 0
T174 0 26 0 0
T175 0 9 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0
T197 0 4 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3288 0 0
T25 10516 0 0 0
T52 0 37 0 0
T61 20116 2 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 39 0 0
T120 14363 0 0 0
T122 0 4 0 0
T127 22125 0 0 0
T171 0 48 0 0
T172 0 17 0 0
T173 0 26 0 0
T174 0 38 0 0
T175 0 20 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0
T198 0 3 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3198 0 0
T25 10516 0 0 0
T52 0 29 0 0
T61 20116 33 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 84 0 0
T120 14363 0 0 0
T122 0 15 0 0
T127 22125 0 0 0
T171 0 50 0 0
T172 0 28 0 0
T173 0 26 0 0
T174 0 29 0 0
T175 0 38 0 0
T176 0 5 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3245 0 0
T52 0 29 0 0
T66 79638 0 0 0
T75 0 80 0 0
T88 2648 0 0 0
T115 0 74 0 0
T122 31153 9 0 0
T141 2710 0 0 0
T171 0 59 0 0
T172 0 24 0 0
T173 0 33 0 0
T174 0 25 0 0
T175 0 15 0 0
T176 0 3 0 0
T181 8199 0 0 0
T182 2639 0 0 0
T183 13769 0 0 0
T184 3163 0 0 0
T185 2825 0 0 0
T186 3199 0 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3084 0 0
T25 10516 0 0 0
T52 0 39 0 0
T61 20116 13 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 81 0 0
T115 0 77 0 0
T120 14363 0 0 0
T122 0 21 0 0
T127 22125 0 0 0
T171 0 54 0 0
T173 0 30 0 0
T174 0 38 0 0
T175 0 7 0 0
T176 0 10 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3212 0 0
T25 10516 0 0 0
T52 0 24 0 0
T61 20116 15 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 78 0 0
T120 14363 0 0 0
T122 0 6 0 0
T127 22125 0 0 0
T171 0 74 0 0
T172 0 18 0 0
T173 0 28 0 0
T174 0 21 0 0
T175 0 24 0 0
T176 0 9 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26690436 3258 0 0
T25 10516 0 0 0
T52 0 14 0 0
T61 20116 16 0 0
T62 8233 0 0 0
T65 33056 0 0 0
T75 0 100 0 0
T120 14363 0 0 0
T122 0 26 0 0
T127 22125 0 0 0
T171 0 62 0 0
T172 0 20 0 0
T173 0 36 0 0
T174 0 35 0 0
T175 0 17 0 0
T177 5722 0 0 0
T178 18073 0 0 0
T179 4955 0 0 0
T180 19440 0 0 0
T199 0 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%