Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3074867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

609707

1

T1

419

T2

138

T3

156

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3273490	1			T1	627		T2	1488		T3	696
values[0x0]	204602	1			T1	189		T2	40		T3	35
values[0x1]	206482	1			T1	165		T2	52		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2108645	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1575929

1

T1

561

T2

555

T3

343

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17673	1			T1	1		T2	4		T3	1
valid_sources[0x01]	11663	1			T1	17		T2	13		T3	6
valid_sources[0x02]	15778	1			T1	13		T3	2		T16	7
valid_sources[0x03]	12991	1			T2	1		T3	6		T16	2
valid_sources[0x04]	16176	1			T1	1		T3	3		T16	5
valid_sources[0x05]	14513	1			T1	5		T2	13		T3	1
valid_sources[0x06]	10361	1			T1	3		T2	4		T16	2
valid_sources[0x07]	11275	1			T1	16		T2	22		T3	2
valid_sources[0x08]	10969	1			T1	2		T2	5		T3	4
valid_sources[0x09]	12336	1			T2	11		T3	7		T16	1
valid_sources[0x0a]	12325	1			T2	10		T3	4		T16	2
valid_sources[0x0b]	11622	1			T1	3		T2	4		T3	4
valid_sources[0x0c]	11468	1			T2	6		T16	1		T17	20
valid_sources[0x0d]	12591	1			T1	3		T2	2		T3	2
valid_sources[0x0e]	11379	1			T1	9		T2	21		T3	5
valid_sources[0x0f]	11523	1			T1	2		T2	9		T3	1
valid_sources[0x10]	11643	1			T1	10		T2	17		T3	7
valid_sources[0x11]	11994	1			T3	3		T16	3		T17	14
valid_sources[0x12]	11631	1			T2	7		T3	7		T17	7
valid_sources[0x13]	13871	1			T1	4		T2	5		T3	2
valid_sources[0x14]	13100	1			T1	23		T2	6		T3	1
valid_sources[0x15]	12552	1			T1	7		T2	12		T3	5
valid_sources[0x16]	14707	1			T1	14		T3	5		T16	8
valid_sources[0x17]	12716	1			T1	10		T16	3		T17	15
valid_sources[0x18]	14791	1			T1	11		T3	6		T16	2
valid_sources[0x19]	12081	1			T1	13		T2	8		T16	3
valid_sources[0x1a]	12695	1			T1	3		T2	1		T3	4
valid_sources[0x1b]	16230	1			T2	10		T3	5		T16	2
valid_sources[0x1c]	11493	1			T1	3		T2	3		T3	2
valid_sources[0x1d]	14651	1			T1	2		T2	1		T3	3
valid_sources[0x1e]	14262	1			T1	9		T3	6		T16	6
valid_sources[0x1f]	12408	1			T3	1		T16	3		T17	10
valid_sources[0x20]	11977	1			T1	8		T3	3		T17	12
valid_sources[0x21]	12720	1			T2	2		T3	2		T16	2
valid_sources[0x22]	16205	1			T2	3		T16	3		T17	10
valid_sources[0x23]	11529	1			T1	2		T2	3		T3	4
valid_sources[0x24]	11210	1			T3	3		T16	6		T17	16
valid_sources[0x25]	11497	1			T1	2		T2	20		T3	2
valid_sources[0x26]	11030	1			T2	10		T3	4		T16	2
valid_sources[0x27]	12000	1			T1	2		T2	12		T3	7
valid_sources[0x28]	11353	1			T2	2		T3	1		T16	14
valid_sources[0x29]	12540	1			T1	10		T2	1		T3	2
valid_sources[0x2a]	12423	1			T2	4		T16	9		T17	9
valid_sources[0x2b]	11220	1			T16	6		T17	6		T18	5
valid_sources[0x2c]	11965	1			T1	2		T2	4		T3	3
valid_sources[0x2d]	11123	1			T1	5		T2	26		T3	5
valid_sources[0x2e]	29918	1			T2	9		T3	3		T16	2
valid_sources[0x2f]	11221	1			T1	1		T3	3		T16	5
valid_sources[0x30]	12260	1			T1	4		T2	10		T16	4
valid_sources[0x31]	10944	1			T1	1		T3	1		T16	5
valid_sources[0x32]	13700	1			T1	2		T3	2		T16	2
valid_sources[0x33]	11150	1			T1	2		T2	5		T3	1
valid_sources[0x34]	12038	1			T1	1		T2	8		T3	5
valid_sources[0x35]	11115	1			T1	4		T2	1		T3	1
valid_sources[0x36]	11192	1			T2	7		T3	3		T17	13
valid_sources[0x37]	11995	1			T1	6		T3	5		T16	1
valid_sources[0x38]	12314	1			T2	1		T16	2		T17	5
valid_sources[0x39]	12139	1			T2	6		T3	2		T17	12
valid_sources[0x3a]	11999	1			T1	9		T2	9		T3	1
valid_sources[0x3b]	13133	1			T1	5		T2	6		T3	4
valid_sources[0x3c]	30791	1			T1	2		T3	2		T16	4
valid_sources[0x3d]	10888	1			T3	4		T16	1		T17	13
valid_sources[0x3e]	11541	1			T1	3		T2	2		T17	6
valid_sources[0x3f]	11914	1			T2	2		T16	4		T17	5
valid_sources[0x40]	12982	1			T1	1		T2	11		T3	5
valid_sources[0x41]	15600	1			T2	2		T3	2		T16	3
valid_sources[0x42]	12476	1			T1	4		T2	3		T3	4
valid_sources[0x43]	10830	1			T1	9		T3	2		T16	7
valid_sources[0x44]	12083	1			T2	4		T3	2		T16	7
valid_sources[0x45]	11815	1			T1	8		T2	20		T3	1
valid_sources[0x46]	11819	1			T1	3		T2	11		T3	4
valid_sources[0x47]	17628	1			T1	2		T2	2		T3	1
valid_sources[0x48]	19202	1			T2	6		T3	7		T16	9
valid_sources[0x49]	11136	1			T2	8		T3	4		T16	2
valid_sources[0x4a]	12019	1			T2	10		T16	1		T17	8
valid_sources[0x4b]	19484	1			T1	1		T2	9		T3	2
valid_sources[0x4c]	11547	1			T1	6		T2	13		T3	4
valid_sources[0x4d]	12092	1			T1	2		T2	1		T16	10
valid_sources[0x4e]	12785	1			T1	8		T2	23		T3	3
valid_sources[0x4f]	11206	1			T1	3		T2	9		T3	1
valid_sources[0x50]	11963	1			T1	1		T2	3		T3	1
valid_sources[0x51]	17760	1			T2	13		T16	6		T17	8
valid_sources[0x52]	12048	1			T1	2		T2	3		T3	1
valid_sources[0x53]	12978	1			T2	7		T3	2		T16	1
valid_sources[0x54]	11849	1			T1	3		T2	1		T3	4
valid_sources[0x55]	11440	1			T1	10		T2	11		T3	2
valid_sources[0x56]	11090	1			T1	8		T2	6		T3	5
valid_sources[0x57]	13037	1			T2	12		T3	2		T16	3
valid_sources[0x58]	11482	1			T1	9		T2	3		T3	3
valid_sources[0x59]	11623	1			T1	8		T2	15		T3	4
valid_sources[0x5a]	11111	1			T3	7		T16	7		T17	7
valid_sources[0x5b]	20745	1			T2	5		T3	5		T16	2
valid_sources[0x5c]	87580	1			T1	11		T2	3		T17	14
valid_sources[0x5d]	13191	1			T1	2		T2	5		T16	5
valid_sources[0x5e]	12437	1			T3	5		T16	2		T17	13
valid_sources[0x5f]	13353	1			T1	13		T2	10		T3	7
valid_sources[0x60]	13964	1			T1	2		T3	3		T16	5
valid_sources[0x61]	14241	1			T2	9		T3	6		T16	3
valid_sources[0x62]	10950	1			T1	10		T2	1		T16	7
valid_sources[0x63]	13051	1			T1	2		T2	3		T3	4
valid_sources[0x64]	11734	1			T1	5		T2	5		T16	3
valid_sources[0x65]	11553	1			T1	1		T2	2		T3	8
valid_sources[0x66]	11358	1			T1	2		T2	10		T3	1
valid_sources[0x67]	11343	1			T1	6		T2	2		T3	1
valid_sources[0x68]	11747	1			T2	5		T3	2		T16	4
valid_sources[0x69]	12677	1			T1	10		T2	6		T3	3
valid_sources[0x6a]	11925	1			T1	9		T3	1		T16	2
valid_sources[0x6b]	11064	1			T3	4		T16	2		T17	7
valid_sources[0x6c]	14050	1			T1	1		T2	3		T3	3
valid_sources[0x6d]	11651	1			T2	13		T3	2		T16	1
valid_sources[0x6e]	43372	1			T1	2		T2	3		T3	3
valid_sources[0x6f]	10766	1			T1	6		T2	4		T3	1
valid_sources[0x70]	11016	1			T1	8		T3	7		T16	5
valid_sources[0x71]	15012	1			T1	1		T2	15		T3	2
valid_sources[0x72]	12748	1			T2	8		T3	5		T16	2
valid_sources[0x73]	11899	1			T3	3		T16	4		T17	14
valid_sources[0x74]	11654	1			T1	1		T2	11		T3	3
valid_sources[0x75]	12647	1			T1	3		T16	4		T17	10
valid_sources[0x76]	15308	1			T16	5		T17	18		T19	3
valid_sources[0x77]	13321	1			T1	8		T2	7		T3	10
valid_sources[0x78]	18939	1			T2	19		T3	2		T17	11
valid_sources[0x79]	11677	1			T1	2		T2	8		T3	5
valid_sources[0x7a]	14042	1			T2	4		T3	7		T16	2
valid_sources[0x7b]	36604	1			T1	1		T3	4		T16	5
valid_sources[0x7c]	12469	1			T1	1		T2	2		T16	3
valid_sources[0x7d]	11233	1			T2	5		T3	3		T16	3
valid_sources[0x7e]	12915	1			T3	1		T16	12		T17	21
valid_sources[0x7f]	11647	1			T2	7		T16	4		T17	5
valid_sources[0x80]	10768	1			T1	4		T3	3		T17	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

330028

1

T1

194

T2

120

T3

128

values[0x0]

all_enables

biggest_size

147303

1

T1

130

T2

12

T3

18

values[0x1]

all_enables

biggest_size

132376

1

T1

95

T2

6

T3

10