Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
24561811 |
24399541 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
24561811 |
24399541 |
0 |
0 |
T1 |
5179 |
5015 |
0 |
0 |
T2 |
21788 |
21726 |
0 |
0 |
T3 |
3103 |
3019 |
0 |
0 |
T4 |
2657 |
2526 |
0 |
0 |
T5 |
18789 |
18724 |
0 |
0 |
T6 |
2684 |
2585 |
0 |
0 |
T16 |
2917 |
2846 |
0 |
0 |
T17 |
8070 |
7995 |
0 |
0 |
T18 |
4877 |
4798 |
0 |
0 |
T19 |
15205 |
15023 |
0 |
0 |