Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2731845	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

578179

1

T1

208

T2

149

T3

185

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2922060	1			T1	654		T2	1811		T3	8816
values[0x0]	192613	1			T1	61		T2	46		T3	55
values[0x1]	195351	1			T1	70		T2	40		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1876178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1433846

1

T1

364

T2

709

T3

3029

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17657	1			T1	2		T3	16		T13	3
valid_sources[0x01]	10558	1			T1	5		T3	9		T13	1
valid_sources[0x02]	10360	1			T1	5		T3	11		T13	4
valid_sources[0x03]	11188	1			T1	2		T3	20		T13	3
valid_sources[0x04]	11869	1			T1	3		T3	19		T13	2
valid_sources[0x05]	10059	1			T1	3		T3	45		T13	5
valid_sources[0x06]	10247	1			T1	2		T3	53		T13	5
valid_sources[0x07]	9838	1			T1	2		T3	38		T13	1
valid_sources[0x08]	12533	1			T1	4		T3	58		T13	4
valid_sources[0x09]	15453	1			T1	3		T3	41		T13	1
valid_sources[0x0a]	13138	1			T1	2		T3	33		T13	4
valid_sources[0x0b]	19019	1			T1	4		T3	27		T13	7
valid_sources[0x0c]	10331	1			T3	18		T13	2		T4	4
valid_sources[0x0d]	18492	1			T1	3		T3	62		T13	2
valid_sources[0x0e]	11735	1			T1	1		T3	41		T13	7
valid_sources[0x0f]	14458	1			T1	3		T3	26		T13	1
valid_sources[0x10]	10040	1			T1	3		T3	13		T13	8
valid_sources[0x11]	11158	1			T1	2		T3	16		T13	6
valid_sources[0x12]	10114	1			T1	6		T3	30		T13	3
valid_sources[0x13]	10163	1			T1	5		T3	26		T13	3
valid_sources[0x14]	10918	1			T1	4		T3	20		T13	5
valid_sources[0x15]	17646	1			T3	27		T13	3		T4	3
valid_sources[0x16]	10300	1			T1	1		T3	37		T13	5
valid_sources[0x17]	10115	1			T1	2		T3	39		T13	3
valid_sources[0x18]	18830	1			T1	2		T3	31		T13	3
valid_sources[0x19]	11545	1			T1	2		T3	45		T13	4
valid_sources[0x1a]	13842	1			T1	4		T3	53		T13	3
valid_sources[0x1b]	11031	1			T3	10		T4	3		T14	43
valid_sources[0x1c]	10469	1			T1	4		T3	24		T13	1
valid_sources[0x1d]	11294	1			T1	3		T3	34		T13	8
valid_sources[0x1e]	10190	1			T3	26		T13	3		T4	2
valid_sources[0x1f]	11518	1			T1	1		T3	29		T13	7
valid_sources[0x20]	10547	1			T3	35		T13	6		T14	27
valid_sources[0x21]	17844	1			T3	82		T13	7		T4	2
valid_sources[0x22]	14895	1			T1	2		T3	44		T13	7
valid_sources[0x23]	9599	1			T3	74		T13	9		T4	1
valid_sources[0x24]	9932	1			T1	1		T3	42		T13	3
valid_sources[0x25]	10592	1			T3	20		T13	4		T4	1
valid_sources[0x26]	10087	1			T3	16		T13	8		T4	6
valid_sources[0x27]	9981	1			T1	4		T3	21		T13	3
valid_sources[0x28]	9614	1			T1	4		T3	20		T13	2
valid_sources[0x29]	12212	1			T1	2		T3	53		T13	3
valid_sources[0x2a]	9808	1			T1	3		T3	27		T13	7
valid_sources[0x2b]	53195	1			T1	7		T3	47		T13	5
valid_sources[0x2c]	11082	1			T1	8		T3	25		T13	1
valid_sources[0x2d]	10295	1			T1	2		T3	41		T13	5
valid_sources[0x2e]	14196	1			T1	3		T3	26		T13	2
valid_sources[0x2f]	13033	1			T1	1		T3	44		T13	3
valid_sources[0x30]	10649	1			T3	44		T13	3		T14	33
valid_sources[0x31]	9886	1			T1	1		T3	32		T13	3
valid_sources[0x32]	9864	1			T3	43		T13	1		T4	1
valid_sources[0x33]	11227	1			T1	11		T3	23		T13	4
valid_sources[0x34]	16338	1			T1	3		T3	41		T13	4
valid_sources[0x35]	14838	1			T1	8		T3	29		T13	2
valid_sources[0x36]	11202	1			T1	4		T3	21		T13	2
valid_sources[0x37]	10263	1			T1	2		T3	21		T13	4
valid_sources[0x38]	13746	1			T1	5		T3	65		T13	7
valid_sources[0x39]	13720	1			T1	1		T3	19		T13	3
valid_sources[0x3a]	10153	1			T1	2		T3	15		T13	5
valid_sources[0x3b]	13071	1			T1	2		T3	31		T13	4
valid_sources[0x3c]	11139	1			T1	6		T3	55		T13	5
valid_sources[0x3d]	12647	1			T1	4		T3	25		T13	2
valid_sources[0x3e]	14177	1			T1	2		T3	51		T13	4
valid_sources[0x3f]	9794	1			T1	2		T3	23		T13	6
valid_sources[0x40]	11329	1			T3	15		T13	5		T4	3
valid_sources[0x41]	10323	1			T1	1		T3	27		T13	3
valid_sources[0x42]	10061	1			T1	4		T3	33		T13	3
valid_sources[0x43]	10083	1			T1	4		T3	33		T13	7
valid_sources[0x44]	12441	1			T1	1		T3	24		T13	4
valid_sources[0x45]	10706	1			T1	4		T3	19		T13	3
valid_sources[0x46]	16580	1			T1	10		T3	22		T13	3
valid_sources[0x47]	10001	1			T1	1		T3	25		T13	5
valid_sources[0x48]	10837	1			T1	4		T3	19		T13	7
valid_sources[0x49]	13111	1			T1	3		T3	34		T13	6
valid_sources[0x4a]	12094	1			T1	4		T2	1897		T3	60
valid_sources[0x4b]	22200	1			T1	13		T3	39		T13	4
valid_sources[0x4c]	9762	1			T1	1		T3	59		T13	2
valid_sources[0x4d]	10127	1			T1	7		T3	35		T13	4
valid_sources[0x4e]	11474	1			T1	2		T3	49		T13	5
valid_sources[0x4f]	10472	1			T1	7		T3	43		T13	2
valid_sources[0x50]	10452	1			T1	2		T3	53		T13	1
valid_sources[0x51]	11263	1			T1	5		T3	11		T13	6
valid_sources[0x52]	10243	1			T1	2		T3	51		T13	3
valid_sources[0x53]	10242	1			T1	6		T3	53		T13	4
valid_sources[0x54]	14180	1			T1	7		T3	32		T13	3
valid_sources[0x55]	11264	1			T1	2		T3	26		T13	6
valid_sources[0x56]	9508	1			T1	2		T3	23		T13	4
valid_sources[0x57]	10002	1			T1	3		T3	27		T13	1
valid_sources[0x58]	10725	1			T1	4		T3	43		T13	4
valid_sources[0x59]	13181	1			T3	42		T13	1		T14	58
valid_sources[0x5a]	11458	1			T1	7		T3	17		T13	8
valid_sources[0x5b]	10703	1			T1	6		T3	31		T13	5
valid_sources[0x5c]	9996	1			T1	4		T3	16		T13	4
valid_sources[0x5d]	10438	1			T1	5		T3	24		T13	4
valid_sources[0x5e]	10102	1			T1	2		T3	11		T13	1
valid_sources[0x5f]	10641	1			T1	7		T3	51		T13	1
valid_sources[0x60]	10146	1			T1	4		T3	57		T13	7
valid_sources[0x61]	10833	1			T1	2		T3	18		T13	4
valid_sources[0x62]	10387	1			T1	3		T3	20		T13	4
valid_sources[0x63]	10700	1			T1	1		T3	53		T13	2
valid_sources[0x64]	13971	1			T1	1		T3	25		T13	5
valid_sources[0x65]	22386	1			T1	6		T3	60		T13	6
valid_sources[0x66]	11584	1			T1	1		T3	15		T13	7
valid_sources[0x67]	14595	1			T1	2		T3	8		T13	9
valid_sources[0x68]	9993	1			T1	2		T3	9		T13	2
valid_sources[0x69]	10319	1			T1	3		T3	50		T13	3
valid_sources[0x6a]	10716	1			T1	4		T3	43		T13	1
valid_sources[0x6b]	10221	1			T1	4		T3	28		T13	3
valid_sources[0x6c]	10351	1			T3	28		T13	4		T4	3
valid_sources[0x6d]	10055	1			T1	7		T3	32		T13	5
valid_sources[0x6e]	63980	1			T3	18		T13	5		T14	73
valid_sources[0x6f]	9694	1			T1	1		T3	27		T13	4
valid_sources[0x70]	10242	1			T3	28		T13	4		T4	1
valid_sources[0x71]	11177	1			T1	1		T3	10		T13	2
valid_sources[0x72]	10187	1			T1	2		T3	48		T13	3
valid_sources[0x73]	14994	1			T1	3		T3	35		T13	7
valid_sources[0x74]	10293	1			T1	1		T3	30		T13	5
valid_sources[0x75]	10156	1			T1	3		T3	14		T13	4
valid_sources[0x76]	13867	1			T1	2		T3	28		T13	5
valid_sources[0x77]	9318	1			T1	5		T3	32		T13	8
valid_sources[0x78]	9909	1			T1	6		T3	20		T13	2
valid_sources[0x79]	10641	1			T1	9		T3	51		T13	2
valid_sources[0x7a]	10540	1			T1	1		T3	43		T13	1
valid_sources[0x7b]	11823	1			T3	62		T13	3		T4	2
valid_sources[0x7c]	9749	1			T1	6		T3	49		T13	8
valid_sources[0x7d]	10285	1			T1	3		T3	26		T13	7
valid_sources[0x7e]	30990	1			T1	7		T3	38		T13	4
valid_sources[0x7f]	12100	1			T1	4		T3	12		T13	4
valid_sources[0x80]	12612	1			T1	5		T3	9		T13	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

313328

1

T1

166

T2

120

T3

154

values[0x0]

all_enables

biggest_size

139008

1

T1

31

T2

19

T3

22

values[0x1]

all_enables

biggest_size

125843

1

T1

11

T2

10

T3

9