SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3346811 | 0 | T1 | 785 | T2 | 1897 | T3 | 8920 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3346598 | 1 | T1 | 785 | T2 | 1897 | T3 | 8920 | ||||
values[1] | 24 | 1 | T131 | 1 | T395 | 1 | T396 | 1 | ||||
values[2] | 6 | 1 | T148 | 1 | T167 | 1 | T397 | 1 | ||||
values[3] | 110 | 1 | T398 | 1 | T64 | 1 | T170 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3346584 | 1 | T1 | 784 | T2 | 1897 | T3 | 8920 | ||||
values[1] | 23 | 1 | T399 | 1 | T148 | 1 | T163 | 2 | ||||
values[2] | 8 | 1 | T400 | 1 | T148 | 2 | T163 | 1 | ||||
values[3] | 105 | 1 | T1 | 1 | T14 | 1 | T54 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3346472 | 1 | T1 | 784 | T2 | 1897 | T3 | 8920 | ||||
auto[TlIntgErrCmd] | 112 | 1 | T398 | 1 | T64 | 1 | T128 | 1 | ||||
auto[TlIntgErrData] | 126 | 1 | T1 | 1 | T14 | 1 | T60 | 1 | ||||
auto[TlIntgErrBoth] | 101 | 1 | T170 | 1 | T129 | 1 | T131 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |