Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
19681574 |
19523963 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19681574 |
19523963 |
0 |
0 |
T1 |
13660 |
13525 |
0 |
0 |
T2 |
23176 |
23109 |
0 |
0 |
T3 |
37659 |
37587 |
0 |
0 |
T4 |
5805 |
5713 |
0 |
0 |
T13 |
3601 |
3411 |
0 |
0 |
T14 |
70545 |
70412 |
0 |
0 |
T15 |
7781 |
7694 |
0 |
0 |
T16 |
99071 |
98995 |
0 |
0 |
T17 |
9477 |
9413 |
0 |
0 |
T18 |
82212 |
82142 |
0 |
0 |