Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2738166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

612889

1

T1

1759

T2

3957

T3

225

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2931189	1			T1	6978		T2	3919		T3	2158
values[0x0]	208376	1			T1	582		T2	1217		T3	69
values[0x1]	211490	1			T1	611		T2	1500		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1881437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1469618

1

T1

3742

T2

4666

T3

853

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10855	1			T1	37		T2	11		T3	12
valid_sources[0x01]	11180	1			T1	36		T2	28		T3	5
valid_sources[0x02]	10840	1			T1	27		T2	42		T3	13
valid_sources[0x03]	13057	1			T1	38		T2	24		T3	6
valid_sources[0x04]	11220	1			T1	36		T2	21		T3	23
valid_sources[0x05]	11751	1			T1	46		T2	23		T3	10
valid_sources[0x06]	9252	1			T1	19		T2	40		T3	6
valid_sources[0x07]	9431	1			T1	33		T2	19		T3	3
valid_sources[0x08]	10480	1			T1	17		T2	22		T3	13
valid_sources[0x09]	10904	1			T1	45		T2	31		T3	7
valid_sources[0x0a]	10892	1			T1	21		T2	22		T3	4
valid_sources[0x0b]	9669	1			T1	32		T2	29		T3	10
valid_sources[0x0c]	10098	1			T1	32		T2	31		T3	12
valid_sources[0x0d]	12913	1			T1	24		T2	18		T3	14
valid_sources[0x0e]	9549	1			T1	24		T2	24		T3	7
valid_sources[0x0f]	9919	1			T1	23		T2	22		T3	4
valid_sources[0x10]	9640	1			T1	32		T2	30		T3	9
valid_sources[0x11]	10461	1			T1	34		T2	27		T3	1
valid_sources[0x12]	10258	1			T1	19		T2	41		T3	9
valid_sources[0x13]	21415	1			T1	26		T2	39		T3	13
valid_sources[0x14]	11543	1			T1	21		T2	18		T3	14
valid_sources[0x15]	10003	1			T1	43		T2	24		T3	12
valid_sources[0x16]	10124	1			T1	29		T2	22		T3	1
valid_sources[0x17]	10970	1			T1	22		T2	26		T3	11
valid_sources[0x18]	12005	1			T1	18		T2	39		T3	2
valid_sources[0x19]	9967	1			T1	40		T2	23		T3	7
valid_sources[0x1a]	9894	1			T1	27		T2	25		T3	10
valid_sources[0x1b]	10322	1			T1	18		T2	16		T3	1
valid_sources[0x1c]	9434	1			T1	28		T2	24		T3	9
valid_sources[0x1d]	12729	1			T1	20		T2	14		T3	8
valid_sources[0x1e]	46088	1			T1	41		T2	25		T3	8
valid_sources[0x1f]	10332	1			T1	33		T2	20		T3	19
valid_sources[0x20]	10649	1			T1	43		T2	24		T3	2
valid_sources[0x21]	10248	1			T1	26		T2	17		T3	9
valid_sources[0x22]	10943	1			T1	27		T2	28		T3	10
valid_sources[0x23]	11381	1			T1	25		T2	20		T3	15
valid_sources[0x24]	46381	1			T1	37		T2	34		T3	2
valid_sources[0x25]	11218	1			T1	37		T2	36		T3	2
valid_sources[0x26]	12936	1			T1	28		T2	24		T3	22
valid_sources[0x27]	9834	1			T1	18		T2	34		T3	4
valid_sources[0x28]	10417	1			T1	45		T2	27		T3	8
valid_sources[0x29]	25417	1			T1	44		T2	24		T3	14
valid_sources[0x2a]	10439	1			T1	31		T2	28		T3	10
valid_sources[0x2b]	10216	1			T1	9		T2	20		T3	6
valid_sources[0x2c]	11066	1			T1	23		T2	17		T3	12
valid_sources[0x2d]	13840	1			T1	24		T2	32		T3	17
valid_sources[0x2e]	9585	1			T1	20		T2	13		T3	6
valid_sources[0x2f]	10867	1			T1	40		T2	40		T3	18
valid_sources[0x30]	10554	1			T1	32		T2	29		T3	13
valid_sources[0x31]	12624	1			T1	35		T2	20		T3	1
valid_sources[0x32]	11149	1			T1	56		T2	20		T3	5
valid_sources[0x33]	11352	1			T1	26		T2	35		T3	9
valid_sources[0x34]	13316	1			T1	32		T2	28		T3	8
valid_sources[0x35]	10133	1			T1	48		T2	32		T3	8
valid_sources[0x36]	10236	1			T1	30		T2	21		T3	2
valid_sources[0x37]	9682	1			T1	26		T2	19		T3	2
valid_sources[0x38]	10380	1			T1	30		T2	39		T3	8
valid_sources[0x39]	10191	1			T1	40		T2	37		T3	7
valid_sources[0x3a]	10399	1			T1	23		T2	14		T3	11
valid_sources[0x3b]	10431	1			T1	22		T2	28		T3	3
valid_sources[0x3c]	18996	1			T1	25		T2	31		T3	5
valid_sources[0x3d]	10816	1			T1	41		T2	17		T3	16
valid_sources[0x3e]	11495	1			T1	44		T2	26		T3	8
valid_sources[0x3f]	11861	1			T1	22		T2	33		T3	7
valid_sources[0x40]	11260	1			T1	27		T2	42		T3	10
valid_sources[0x41]	11571	1			T1	38		T2	33		T3	12
valid_sources[0x42]	10551	1			T1	39		T2	25		T3	7
valid_sources[0x43]	10467	1			T1	48		T2	12		T3	2
valid_sources[0x44]	10715	1			T1	22		T2	34		T3	9
valid_sources[0x45]	11255	1			T1	37		T2	33		T3	4
valid_sources[0x46]	11201	1			T1	25		T2	25		T3	14
valid_sources[0x47]	9854	1			T1	52		T2	24		T3	6
valid_sources[0x48]	22710	1			T1	25		T2	30		T3	6
valid_sources[0x49]	12614	1			T1	22		T2	15		T3	8
valid_sources[0x4a]	9883	1			T1	33		T2	42		T3	9
valid_sources[0x4b]	28070	1			T1	21		T2	34		T3	10
valid_sources[0x4c]	9852	1			T1	19		T2	27		T3	10
valid_sources[0x4d]	10040	1			T1	38		T2	18		T3	12
valid_sources[0x4e]	14292	1			T1	27		T2	36		T3	11
valid_sources[0x4f]	10599	1			T1	26		T2	26		T3	3
valid_sources[0x50]	15360	1			T1	25		T2	43		T3	6
valid_sources[0x51]	9711	1			T1	27		T2	23		T3	21
valid_sources[0x52]	12926	1			T1	38		T2	27		T3	7
valid_sources[0x53]	9856	1			T1	42		T2	19		T3	1
valid_sources[0x54]	10611	1			T1	27		T2	19		T3	13
valid_sources[0x55]	10315	1			T1	50		T2	20		T3	18
valid_sources[0x56]	10386	1			T1	31		T2	25		T3	5
valid_sources[0x57]	28021	1			T1	32		T2	8		T3	15
valid_sources[0x58]	10391	1			T1	30		T2	30		T3	2
valid_sources[0x59]	11002	1			T1	33		T2	16		T3	4
valid_sources[0x5a]	12233	1			T1	68		T2	29		T3	6
valid_sources[0x5b]	13483	1			T1	32		T2	32		T3	8
valid_sources[0x5c]	10892	1			T1	37		T2	19		T3	24
valid_sources[0x5d]	18734	1			T1	24		T2	35		T3	5
valid_sources[0x5e]	63308	1			T1	54		T2	27		T3	6
valid_sources[0x5f]	10343	1			T1	28		T2	26		T3	25
valid_sources[0x60]	9436	1			T1	37		T2	13		T3	10
valid_sources[0x61]	10679	1			T1	27		T2	35		T3	5
valid_sources[0x62]	9810	1			T1	22		T2	32		T3	9
valid_sources[0x63]	10712	1			T1	30		T2	50		T3	8
valid_sources[0x64]	9775	1			T1	44		T2	33		T3	5
valid_sources[0x65]	9788	1			T1	40		T2	33		T3	10
valid_sources[0x66]	11662	1			T1	38		T2	23		T3	13
valid_sources[0x67]	11073	1			T1	43		T2	15		T3	4
valid_sources[0x68]	10557	1			T1	39		T2	30		T3	8
valid_sources[0x69]	11162	1			T1	26		T2	28		T3	2
valid_sources[0x6a]	9967	1			T1	29		T2	23		T3	18
valid_sources[0x6b]	10597	1			T1	31		T2	11		T3	12
valid_sources[0x6c]	9758	1			T1	36		T2	22		T3	8
valid_sources[0x6d]	9628	1			T1	42		T2	33		T3	12
valid_sources[0x6e]	13344	1			T1	41		T2	19		T3	13
valid_sources[0x6f]	10470	1			T1	37		T2	24		T3	8
valid_sources[0x70]	9797	1			T1	36		T2	35		T3	16
valid_sources[0x71]	9563	1			T1	27		T2	27		T3	14
valid_sources[0x72]	11377	1			T1	31		T2	28		T3	14
valid_sources[0x73]	9657	1			T1	37		T2	21		T3	4
valid_sources[0x74]	14570	1			T1	33		T2	23		T3	3
valid_sources[0x75]	10921	1			T1	15		T2	30		T3	13
valid_sources[0x76]	9898	1			T1	24		T2	22		T3	5
valid_sources[0x77]	9938	1			T1	35		T2	27		T3	1
valid_sources[0x78]	10119	1			T1	24		T2	14		T3	11
valid_sources[0x79]	12217	1			T1	28		T2	41		T3	8
valid_sources[0x7a]	10706	1			T1	43		T2	22		T3	21
valid_sources[0x7b]	11005	1			T1	47		T2	39		T3	4
valid_sources[0x7c]	10421	1			T1	37		T2	30		T3	13
valid_sources[0x7d]	10254	1			T1	33		T2	16		T4	15
valid_sources[0x7e]	10350	1			T1	49		T2	24		T3	2
valid_sources[0x7f]	14433	1			T1	40		T2	40		T3	13
valid_sources[0x80]	16511	1			T1	32		T2	23		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

324202

1

T1

1036

T2

1966

T3

180

values[0x0]

all_enables

biggest_size

151629

1

T1

393

T2

1017

T3

25

values[0x1]

all_enables

biggest_size

137058

1

T1

330

T2

974

T3

20