Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
20522175 |
20364418 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20522175 |
20364418 |
0 |
0 |
T1 |
72625 |
72117 |
0 |
0 |
T2 |
31246 |
31113 |
0 |
0 |
T3 |
6803 |
6751 |
0 |
0 |
T4 |
27844 |
27767 |
0 |
0 |
T15 |
3953 |
3764 |
0 |
0 |
T16 |
604 |
541 |
0 |
0 |
T17 |
3840 |
3740 |
0 |
0 |
T18 |
7031 |
6960 |
0 |
0 |
T19 |
2450 |
2372 |
0 |
0 |
T20 |
7125 |
7033 |
0 |
0 |