Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22308099	16823	0	0
attest_sw_binding_0_rd_A	22308099	3345	0	0
attest_sw_binding_1_rd_A	22308099	3163	0	0
attest_sw_binding_2_rd_A	22308099	3273	0	0
attest_sw_binding_3_rd_A	22308099	3164	0	0
attest_sw_binding_4_rd_A	22308099	3142	0	0
attest_sw_binding_5_rd_A	22308099	3378	0	0
attest_sw_binding_6_rd_A	22308099	3220	0	0
attest_sw_binding_7_rd_A	22308099	3288	0	0
intr_enable_rd_A	22308099	3692	0	0
key_version_rd_A	22308099	3125	0	0
max_creator_key_ver_regwen_rd_A	22308099	3320	0	0
max_owner_int_key_ver_regwen_rd_A	22308099	3255	0	0
max_owner_key_ver_regwen_rd_A	22308099	3359	0	0
reseed_interval_regwen_rd_A	22308099	3192	0	0
salt_0_rd_A	22308099	3135	0	0
salt_1_rd_A	22308099	3057	0	0
salt_2_rd_A	22308099	3269	0	0
salt_3_rd_A	22308099	3278	0	0
salt_4_rd_A	22308099	3476	0	0
salt_5_rd_A	22308099	3438	0	0
salt_6_rd_A	22308099	3278	0	0
salt_7_rd_A	22308099	3273	0	0
sealing_sw_binding_0_rd_A	22308099	3323	0	0
sealing_sw_binding_1_rd_A	22308099	3073	0	0
sealing_sw_binding_2_rd_A	22308099	3352	0	0
sealing_sw_binding_3_rd_A	22308099	3262	0	0
sealing_sw_binding_4_rd_A	22308099	3287	0	0
sealing_sw_binding_5_rd_A	22308099	3308	0	0
sealing_sw_binding_6_rd_A	22308099	3288	0	0
sealing_sw_binding_7_rd_A	22308099	3147	0	0
sideload_clear_rd_A	22308099	3220	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	16823	0	0
T2	31246	1263	0	0
T3	6803	0	0	0
T4	27844	410	0	0
T15	3953	0	0	0
T16	604	0	0	0
T17	3840	0	0	0
T18	7031	0	0	0
T19	2450	0	0	0
T20	7125	0	0	0
T29	0	87	0	0
T38	2457	0	0	0
T54	0	992	0	0
T60	0	478	0	0
T62	0	150	0	0
T72	0	53	0	0
T122	0	79	0	0
T123	0	326	0	0
T164	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3345	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	49	0	0
T64	20839	0	0	0
T72	0	27	0	0
T122	73514	40	0	0
T126	3484	0	0	0
T165	0	54	0	0
T166	0	38	0	0
T167	0	29	0	0
T168	0	47	0	0
T169	0	40	0	0
T170	0	20	0	0
T171	0	4	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3163	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	41	0	0
T64	20839	0	0	0
T72	0	28	0	0
T122	73514	53	0	0
T126	3484	0	0	0
T165	0	37	0	0
T166	0	41	0	0
T167	0	26	0	0
T168	0	37	0	0
T169	0	26	0	0
T170	0	1	0	0
T171	0	6	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3273	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	23	0	0
T64	20839	0	0	0
T72	0	16	0	0
T122	73514	78	0	0
T126	3484	0	0	0
T165	0	38	0	0
T166	0	52	0	0
T167	0	32	0	0
T168	0	55	0	0
T169	0	39	0	0
T170	0	1	0	0
T171	0	8	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3164	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	29	0	0
T64	20839	0	0	0
T72	0	23	0	0
T122	73514	53	0	0
T126	3484	0	0	0
T165	0	21	0	0
T166	0	48	0	0
T167	0	28	0	0
T168	0	32	0	0
T169	0	20	0	0
T170	0	10	0	0
T171	0	6	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3142	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	35	0	0
T64	20839	0	0	0
T72	0	36	0	0
T122	73514	47	0	0
T126	3484	0	0	0
T165	0	40	0	0
T166	0	41	0	0
T167	0	37	0	0
T168	0	37	0	0
T169	0	28	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3378	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	24	0	0
T64	20839	0	0	0
T72	0	19	0	0
T119	0	56	0	0
T122	73514	49	0	0
T126	3484	0	0	0
T165	0	31	0	0
T166	0	36	0	0
T167	0	17	0	0
T168	0	25	0	0
T169	0	15	0	0
T170	0	6	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3220	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	40	0	0
T64	20839	0	0	0
T72	0	28	0	0
T122	73514	40	0	0
T126	3484	0	0	0
T165	0	38	0	0
T166	0	52	0	0
T167	0	32	0	0
T168	0	35	0	0
T169	0	15	0	0
T170	0	21	0	0
T171	0	1	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3288	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	27	0	0
T64	20839	0	0	0
T72	0	31	0	0
T122	73514	51	0	0
T126	3484	0	0	0
T165	0	30	0	0
T166	0	40	0	0
T167	0	46	0	0
T168	0	42	0	0
T169	0	46	0	0
T170	0	6	0	0
T171	0	4	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3692	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	18	0	0
T64	20839	0	0	0
T69	0	35	0	0
T72	0	49	0	0
T122	73514	46	0	0
T126	3484	0	0	0
T165	0	35	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0
T177	0	40	0	0
T178	0	11	0	0
T179	0	14	0	0
T180	0	34	0	0
T181	0	64	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3125	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	24	0	0
T64	20839	0	0	0
T72	0	20	0	0
T122	73514	53	0	0
T126	3484	0	0	0
T165	0	42	0	0
T166	0	24	0	0
T167	0	26	0	0
T168	0	39	0	0
T169	0	9	0	0
T170	0	13	0	0
T171	0	5	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3320	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	31	0	0
T64	20839	0	0	0
T72	0	27	0	0
T122	73514	49	0	0
T126	3484	0	0	0
T165	0	26	0	0
T166	0	42	0	0
T167	0	28	0	0
T168	0	17	0	0
T169	0	43	0	0
T170	0	1	0	0
T171	0	6	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3255	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	36	0	0
T64	20839	0	0	0
T72	0	43	0	0
T119	0	76	0	0
T122	73514	43	0	0
T126	3484	0	0	0
T165	0	27	0	0
T166	0	54	0	0
T167	0	33	0	0
T168	0	25	0	0
T169	0	23	0	0
T171	0	2	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3359	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	16	0	0
T64	20839	0	0	0
T72	0	40	0	0
T122	73514	72	0	0
T126	3484	0	0	0
T165	0	39	0	0
T166	0	74	0	0
T167	0	35	0	0
T168	0	52	0	0
T169	0	32	0	0
T170	0	26	0	0
T171	0	7	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3192	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	24	0	0
T64	20839	0	0	0
T72	0	29	0	0
T122	73514	41	0	0
T126	3484	0	0	0
T165	0	32	0	0
T166	0	40	0	0
T167	0	38	0	0
T168	0	30	0	0
T169	0	27	0	0
T170	0	26	0	0
T171	0	10	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3135	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	64	0	0
T64	20839	7	0	0
T72	0	44	0	0
T122	73514	38	0	0
T126	3484	0	0	0
T165	0	46	0	0
T166	0	42	0	0
T167	0	35	0	0
T168	0	27	0	0
T169	0	36	0	0
T170	0	17	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3057	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	41	0	0
T64	20839	0	0	0
T72	0	22	0	0
T122	73514	51	0	0
T126	3484	0	0	0
T165	0	12	0	0
T166	0	53	0	0
T167	0	29	0	0
T168	0	25	0	0
T169	0	28	0	0
T170	0	14	0	0
T171	0	11	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3269	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	38	0	0
T64	20839	0	0	0
T72	0	25	0	0
T122	73514	61	0	0
T126	3484	0	0	0
T165	0	23	0	0
T166	0	54	0	0
T167	0	47	0	0
T168	0	22	0	0
T169	0	25	0	0
T170	0	18	0	0
T171	0	8	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3278	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	33	0	0
T64	20839	0	0	0
T72	0	29	0	0
T122	73514	57	0	0
T126	3484	0	0	0
T165	0	36	0	0
T166	0	70	0	0
T167	0	30	0	0
T168	0	43	0	0
T169	0	34	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3476	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	20	0	0
T64	20839	0	0	0
T72	0	45	0	0
T122	73514	50	0	0
T126	3484	0	0	0
T165	0	27	0	0
T166	0	47	0	0
T167	0	33	0	0
T168	0	63	0	0
T169	0	21	0	0
T170	0	19	0	0
T171	0	4	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3438	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	34	0	0
T64	20839	0	0	0
T72	0	34	0	0
T122	73514	66	0	0
T126	3484	0	0	0
T165	0	34	0	0
T166	0	50	0	0
T167	0	14	0	0
T168	0	23	0	0
T169	0	28	0	0
T170	0	19	0	0
T171	0	11	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3278	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	32	0	0
T64	20839	0	0	0
T72	0	21	0	0
T122	73514	44	0	0
T126	3484	0	0	0
T165	0	43	0	0
T166	0	60	0	0
T167	0	11	0	0
T168	0	19	0	0
T169	0	43	0	0
T170	0	20	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0
T182	0	4	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3273	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	49	0	0
T64	20839	0	0	0
T72	0	44	0	0
T122	73514	50	0	0
T126	3484	0	0	0
T165	0	30	0	0
T166	0	44	0	0
T167	0	15	0	0
T168	0	35	0	0
T169	0	29	0	0
T170	0	16	0	0
T171	0	14	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3323	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	42	0	0
T64	20839	0	0	0
T72	0	18	0	0
T122	73514	41	0	0
T126	3484	0	0	0
T165	0	25	0	0
T166	0	49	0	0
T167	0	30	0	0
T168	0	15	0	0
T169	0	22	0	0
T170	0	9	0	0
T171	0	8	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3073	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	39	0	0
T64	20839	0	0	0
T72	0	31	0	0
T122	73514	33	0	0
T126	3484	0	0	0
T165	0	34	0	0
T166	0	53	0	0
T167	0	36	0	0
T168	0	49	0	0
T169	0	25	0	0
T170	0	16	0	0
T171	0	12	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3352	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	39	0	0
T64	20839	0	0	0
T72	0	19	0	0
T122	73514	52	0	0
T126	3484	0	0	0
T165	0	28	0	0
T166	0	62	0	0
T167	0	23	0	0
T168	0	53	0	0
T169	0	28	0	0
T170	0	10	0	0
T171	0	5	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3262	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	35	0	0
T64	20839	0	0	0
T72	0	33	0	0
T122	73514	42	0	0
T126	3484	0	0	0
T165	0	27	0	0
T166	0	40	0	0
T167	0	31	0	0
T168	0	54	0	0
T169	0	38	0	0
T170	0	10	0	0
T171	0	3	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3287	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	24	0	0
T64	20839	0	0	0
T72	0	27	0	0
T122	73514	68	0	0
T126	3484	0	0	0
T165	0	13	0	0
T166	0	57	0	0
T167	0	48	0	0
T168	0	24	0	0
T169	0	14	0	0
T170	0	4	0	0
T171	0	8	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3308	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	53	0	0
T64	20839	0	0	0
T72	0	26	0	0
T122	73514	55	0	0
T126	3484	0	0	0
T165	0	21	0	0
T166	0	48	0	0
T167	0	31	0	0
T168	0	26	0	0
T169	0	23	0	0
T170	0	10	0	0
T171	0	4	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3288	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	33	0	0
T64	20839	0	0	0
T72	0	29	0	0
T122	73514	41	0	0
T126	3484	0	0	0
T165	0	19	0	0
T166	0	38	0	0
T167	0	28	0	0
T168	0	27	0	0
T169	0	40	0	0
T170	0	10	0	0
T171	0	11	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3147	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	44	0	0
T64	20839	0	0	0
T72	0	30	0	0
T122	73514	50	0	0
T126	3484	0	0	0
T165	0	27	0	0
T166	0	51	0	0
T167	0	41	0	0
T168	0	30	0	0
T169	0	11	0	0
T170	0	43	0	0
T171	0	16	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22308099	3220	0	0
T53	12306	0	0	0
T60	13962	0	0	0
T62	0	22	0	0
T64	20839	0	0	0
T72	0	50	0	0
T122	73514	42	0	0
T126	3484	0	0	0
T165	0	36	0	0
T166	0	34	0	0
T167	0	28	0	0
T168	0	20	0	0
T169	0	45	0	0
T170	0	3	0	0
T171	0	17	0	0
T172	1710	0	0	0
T173	4201	0	0	0
T174	39459	0	0	0
T175	10812	0	0	0
T176	29488	0	0	0