Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2787568	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

611627

1

T1

376

T2

1

T3

370

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2979454	1			T1	642		T2	1		T3	517
values[0x0]	208115	1			T1	129		T2	1		T3	131
values[0x1]	211626	1			T1	146		T2	3		T3	131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1918293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1480902

1

T1

505

T2

1

T3

464

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9345	1			T1	7		T4	2		T15	6
valid_sources[0x01]	9885	1			T1	9		T4	1		T15	3
valid_sources[0x02]	9233	1			T1	3		T15	5		T16	32
valid_sources[0x03]	9807	1			T1	1		T4	1		T15	9
valid_sources[0x04]	9419	1			T1	1		T15	2		T16	59
valid_sources[0x05]	10484	1			T1	1		T4	2		T15	14
valid_sources[0x06]	10386	1			T4	6		T15	11		T16	45
valid_sources[0x07]	10308	1			T1	2		T4	4		T15	10
valid_sources[0x08]	19749	1			T1	3		T4	3		T15	14
valid_sources[0x09]	16212	1			T1	7		T4	3		T15	4
valid_sources[0x0a]	11700	1			T1	5		T4	1		T15	12
valid_sources[0x0b]	9398	1			T1	6		T4	3		T15	5
valid_sources[0x0c]	13036	1			T1	2		T4	1		T15	13
valid_sources[0x0d]	28735	1			T1	6		T15	5		T16	16
valid_sources[0x0e]	9616	1			T1	1		T4	3		T15	9
valid_sources[0x0f]	18908	1			T1	6		T4	4		T16	37
valid_sources[0x10]	9017	1			T1	1		T4	4		T15	5
valid_sources[0x11]	13862	1			T1	2		T4	3		T15	22
valid_sources[0x12]	11538	1			T1	1		T4	1		T15	5
valid_sources[0x13]	12432	1			T1	3		T4	2		T15	8
valid_sources[0x14]	10662	1			T1	6		T4	3		T15	7
valid_sources[0x15]	9910	1			T1	2		T15	7		T16	31
valid_sources[0x16]	12195	1			T1	4		T4	1		T15	2
valid_sources[0x17]	9703	1			T1	4		T4	3		T15	13
valid_sources[0x18]	9300	1			T1	2		T4	4		T15	9
valid_sources[0x19]	16187	1			T1	5		T2	1		T4	1
valid_sources[0x1a]	52724	1			T1	7		T4	3		T15	8
valid_sources[0x1b]	9959	1			T1	3		T4	2		T15	3
valid_sources[0x1c]	23207	1			T1	11		T4	2		T15	3
valid_sources[0x1d]	11836	1			T1	5		T4	2		T16	24
valid_sources[0x1e]	10111	1			T4	7		T15	3		T16	35
valid_sources[0x1f]	10454	1			T1	3		T4	1		T15	12
valid_sources[0x20]	91222	1			T1	2		T4	1		T15	8
valid_sources[0x21]	11973	1			T1	1		T15	4		T16	27
valid_sources[0x22]	48593	1			T1	3		T4	3		T15	9
valid_sources[0x23]	10512	1			T1	3		T4	2		T15	10
valid_sources[0x24]	10388	1			T1	2		T4	2		T15	7
valid_sources[0x25]	9649	1			T1	3		T4	2		T15	13
valid_sources[0x26]	10431	1			T1	3		T4	2		T15	2
valid_sources[0x27]	14008	1			T1	1		T4	3		T15	10
valid_sources[0x28]	9079	1			T1	4		T4	2		T15	6
valid_sources[0x29]	10880	1			T4	2		T15	18		T16	23
valid_sources[0x2a]	9809	1			T1	2		T4	4		T15	10
valid_sources[0x2b]	24660	1			T1	4		T4	1		T15	3
valid_sources[0x2c]	9822	1			T1	7		T4	3		T15	10
valid_sources[0x2d]	9089	1			T1	1		T4	2		T15	7
valid_sources[0x2e]	10388	1			T1	2		T4	4		T15	7
valid_sources[0x2f]	11088	1			T1	5		T4	3		T15	12
valid_sources[0x30]	9594	1			T1	5		T15	16		T16	26
valid_sources[0x31]	9771	1			T1	4		T4	2		T16	28
valid_sources[0x32]	9855	1			T1	3		T4	1		T15	3
valid_sources[0x33]	15060	1			T1	6		T4	1		T15	6
valid_sources[0x34]	47746	1			T1	4		T4	3		T15	7
valid_sources[0x35]	9726	1			T1	5		T4	1		T15	8
valid_sources[0x36]	10104	1			T1	7		T4	4		T15	18
valid_sources[0x37]	9348	1			T1	3		T4	1		T15	9
valid_sources[0x38]	10483	1			T1	4		T15	4		T16	16
valid_sources[0x39]	9542	1			T1	4		T4	2		T15	4
valid_sources[0x3a]	9390	1			T1	3		T4	5		T15	9
valid_sources[0x3b]	15666	1			T1	7		T4	4		T15	2
valid_sources[0x3c]	9290	1			T1	6		T4	4		T15	5
valid_sources[0x3d]	12799	1			T1	3		T15	9		T16	48
valid_sources[0x3e]	9230	1			T1	3		T4	1		T15	1
valid_sources[0x3f]	10562	1			T1	4		T4	7		T15	2
valid_sources[0x40]	9551	1			T1	1		T4	2		T15	5
valid_sources[0x41]	9514	1			T1	4		T15	15		T16	48
valid_sources[0x42]	10057	1			T1	1		T4	4		T15	4
valid_sources[0x43]	13113	1			T1	3		T4	4		T15	18
valid_sources[0x44]	11053	1			T1	3		T4	1		T15	5
valid_sources[0x45]	12562	1			T1	1		T4	2		T15	2
valid_sources[0x46]	8646	1			T1	4		T4	5		T15	11
valid_sources[0x47]	16658	1			T1	6		T15	12		T16	46
valid_sources[0x48]	19166	1			T1	5		T4	5		T15	6
valid_sources[0x49]	10890	1			T1	4		T4	1		T15	8
valid_sources[0x4a]	14194	1			T1	1		T15	12		T16	42
valid_sources[0x4b]	13141	1			T1	7		T15	11		T16	19
valid_sources[0x4c]	12826	1			T1	6		T4	2		T15	14
valid_sources[0x4d]	17139	1			T1	5		T4	2		T15	6
valid_sources[0x4e]	9292	1			T1	5		T4	3		T15	9
valid_sources[0x4f]	10515	1			T1	1		T4	3		T15	1
valid_sources[0x50]	13486	1			T1	3		T4	3		T15	11
valid_sources[0x51]	10186	1			T1	7		T4	4		T15	2
valid_sources[0x52]	9610	1			T1	6		T4	7		T15	9
valid_sources[0x53]	21009	1			T1	6		T4	3		T15	12
valid_sources[0x54]	9919	1			T1	8		T4	4		T15	7
valid_sources[0x55]	9163	1			T1	4		T4	5		T15	7
valid_sources[0x56]	11159	1			T1	5		T4	1		T15	17
valid_sources[0x57]	9772	1			T1	3		T15	6		T16	66
valid_sources[0x58]	21534	1			T1	1		T15	12		T16	36
valid_sources[0x59]	10084	1			T1	4		T4	6		T15	7
valid_sources[0x5a]	10831	1			T1	3		T15	3		T16	40
valid_sources[0x5b]	15681	1			T15	5		T16	27		T32	1
valid_sources[0x5c]	17856	1			T1	8		T15	5		T16	96
valid_sources[0x5d]	9876	1			T1	3		T15	3		T16	13
valid_sources[0x5e]	13358	1			T1	3		T4	2		T15	2
valid_sources[0x5f]	100766	1			T1	4		T4	3		T15	2
valid_sources[0x60]	10219	1			T1	3		T4	4		T15	4
valid_sources[0x61]	9347	1			T4	5		T15	2		T16	51
valid_sources[0x62]	10272	1			T1	4		T4	2		T15	3
valid_sources[0x63]	9263	1			T1	3		T4	2		T15	4
valid_sources[0x64]	9823	1			T1	2		T4	1		T15	4
valid_sources[0x65]	9961	1			T1	2		T4	4		T15	6
valid_sources[0x66]	13966	1			T1	4		T15	12		T16	24
valid_sources[0x67]	14499	1			T1	2		T4	1		T15	6
valid_sources[0x68]	9943	1			T1	2		T4	4		T15	5
valid_sources[0x69]	12043	1			T1	1		T15	5		T16	43
valid_sources[0x6a]	8897	1			T1	3		T4	2		T15	7
valid_sources[0x6b]	9635	1			T1	4		T4	3		T15	4
valid_sources[0x6c]	11111	1			T1	3		T15	16		T16	43
valid_sources[0x6d]	13757	1			T1	1		T15	15		T16	28
valid_sources[0x6e]	9782	1			T1	4		T4	2		T15	6
valid_sources[0x6f]	33465	1			T1	7		T15	8		T16	33
valid_sources[0x70]	14723	1			T1	5		T4	1		T15	11
valid_sources[0x71]	10103	1			T1	6		T4	1		T15	8
valid_sources[0x72]	9692	1			T1	2		T15	2		T16	22
valid_sources[0x73]	8939	1			T4	7		T15	14		T16	29
valid_sources[0x74]	12071	1			T1	9		T4	3		T15	4
valid_sources[0x75]	9611	1			T1	2		T4	2		T15	7
valid_sources[0x76]	11197	1			T1	3		T4	5		T15	4
valid_sources[0x77]	10732	1			T1	7		T4	1		T15	3
valid_sources[0x78]	10624	1			T1	2		T4	4		T15	6
valid_sources[0x79]	11187	1			T1	3		T4	3		T15	4
valid_sources[0x7a]	16065	1			T1	2		T4	9		T15	11
valid_sources[0x7b]	10790	1			T1	3		T4	2		T15	8
valid_sources[0x7c]	10911	1			T4	2		T15	8		T16	89
valid_sources[0x7d]	11296	1			T1	6		T4	2		T15	6
valid_sources[0x7e]	10997	1			T1	6		T4	2		T15	23
valid_sources[0x7f]	9677	1			T1	3		T4	2		T15	10
valid_sources[0x80]	9804	1			T1	8		T4	6		T15	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326428

1

T1

218

T3

219

T4

104

values[0x0]

all_enables

biggest_size

149481

1

T1

84

T3

83

T4

66

values[0x1]

all_enables

biggest_size

135718

1

T1

74

T2

1

T3

68