Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21069247 |
20899071 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21069247 |
20899071 |
0 |
0 |
T1 |
2681 |
2510 |
0 |
0 |
T2 |
1547 |
1448 |
0 |
0 |
T3 |
8316 |
8242 |
0 |
0 |
T4 |
3382 |
3225 |
0 |
0 |
T5 |
6015 |
5925 |
0 |
0 |
T14 |
5106 |
4955 |
0 |
0 |
T15 |
12437 |
12340 |
0 |
0 |
T16 |
83339 |
83269 |
0 |
0 |
T17 |
38806 |
38055 |
0 |
0 |
T18 |
3589 |
3516 |
0 |
0 |