Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22752379	17621	0	0
attest_sw_binding_0_rd_A	22752379	2033	0	0
attest_sw_binding_1_rd_A	22752379	2217	0	0
attest_sw_binding_2_rd_A	22752379	2222	0	0
attest_sw_binding_3_rd_A	22752379	2130	0	0
attest_sw_binding_4_rd_A	22752379	2220	0	0
attest_sw_binding_5_rd_A	22752379	2145	0	0
attest_sw_binding_6_rd_A	22752379	2176	0	0
attest_sw_binding_7_rd_A	22752379	2095	0	0
intr_enable_rd_A	22752379	2932	0	0
key_version_rd_A	22752379	2191	0	0
max_creator_key_ver_regwen_rd_A	22752379	2144	0	0
max_owner_int_key_ver_regwen_rd_A	22752379	2061	0	0
max_owner_key_ver_regwen_rd_A	22752379	2146	0	0
reseed_interval_regwen_rd_A	22752379	2174	0	0
salt_0_rd_A	22752379	2110	0	0
salt_1_rd_A	22752379	2123	0	0
salt_2_rd_A	22752379	2317	0	0
salt_3_rd_A	22752379	2187	0	0
salt_4_rd_A	22752379	2079	0	0
salt_5_rd_A	22752379	2139	0	0
salt_6_rd_A	22752379	2090	0	0
salt_7_rd_A	22752379	2481	0	0
sealing_sw_binding_0_rd_A	22752379	2207	0	0
sealing_sw_binding_1_rd_A	22752379	2017	0	0
sealing_sw_binding_2_rd_A	22752379	2271	0	0
sealing_sw_binding_3_rd_A	22752379	2095	0	0
sealing_sw_binding_4_rd_A	22752379	2161	0	0
sealing_sw_binding_5_rd_A	22752379	2375	0	0
sealing_sw_binding_6_rd_A	22752379	2114	0	0
sealing_sw_binding_7_rd_A	22752379	2324	0	0
sideload_clear_rd_A	22752379	2275	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	17621	0	0
T7	9534	0	0	0
T47	0	569	0	0
T60	32171	0	0	0
T63	0	300	0	0
T64	0	46	0	0
T66	0	233	0	0
T80	27303	44	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T123	0	391	0	0
T124	0	199	0	0
T125	0	158	0	0
T127	0	138	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T131	0	225	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2033	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	53	0	0
T80	27303	24	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	51	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	5	0	0
T155	0	7	0	0
T162	0	47	0	0
T183	0	23	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	118	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2217	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	50	0	0
T80	27303	29	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	47	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	2	0	0
T155	0	4	0	0
T162	0	51	0	0
T183	0	18	0	0
T185	0	13	0	0
T186	0	130	0	0
T187	0	7	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2222	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	47	0	0
T80	27303	36	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	7	0	0
T155	0	7	0	0
T162	0	48	0	0
T183	0	18	0	0
T184	0	7	0	0
T185	0	3	0	0
T186	0	120	0	0
T188	0	7	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2130	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	40	0	0
T80	27303	33	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	42	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	6	0	0
T162	0	51	0	0
T183	0	17	0	0
T185	0	5	0	0
T186	0	150	0	0
T188	0	10	0	0
T189	0	5	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2220	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	34	0	0
T80	27303	49	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	3	0	0
T162	0	72	0	0
T183	0	14	0	0
T184	0	1	0	0
T185	0	8	0	0
T186	0	133	0	0
T187	0	16	0	0
T188	0	2	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2145	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	47	0	0
T80	27303	13	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	12	0	0
T155	0	12	0	0
T162	0	55	0	0
T183	0	25	0	0
T184	0	3	0	0
T185	0	8	0	0
T186	0	134	0	0
T188	0	2	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2176	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	48	0	0
T80	27303	21	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	41	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	4	0	0
T155	0	1	0	0
T162	0	66	0	0
T183	0	18	0	0
T184	0	12	0	0
T185	0	1	0	0
T186	0	156	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2095	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	54	0	0
T80	27303	25	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	59	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	3	0	0
T155	0	15	0	0
T162	0	59	0	0
T183	0	27	0	0
T184	0	13	0	0
T186	0	114	0	0
T188	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2932	0	0
T7	9534	0	0	0
T46	0	30	0	0
T60	32171	0	0	0
T66	0	141	0	0
T71	0	88	0	0
T80	27303	41	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T162	0	89	0	0
T190	0	5	0	0
T191	0	42	0	0
T192	0	34	0	0
T193	0	9	0	0
T194	0	70	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2191	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	69	0	0
T80	27303	25	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	3	0	0
T155	0	9	0	0
T162	0	48	0	0
T183	0	21	0	0
T184	0	5	0	0
T185	0	12	0	0
T186	0	116	0	0
T187	0	4	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2144	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	67	0	0
T80	27303	47	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	41	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	11	0	0
T162	0	51	0	0
T183	0	16	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	153	0	0
T188	0	6	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2061	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	38	0	0
T80	27303	19	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	41	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	1	0	0
T155	0	6	0	0
T162	0	51	0	0
T183	0	30	0	0
T184	0	2	0	0
T186	0	122	0	0
T188	0	7	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2146	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	40	0	0
T80	27303	26	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	5	0	0
T162	0	46	0	0
T183	0	29	0	0
T184	0	9	0	0
T185	0	10	0	0
T186	0	96	0	0
T187	0	7	0	0
T188	0	15	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2174	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	48	0	0
T80	27303	41	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	1	0	0
T155	0	6	0	0
T162	0	70	0	0
T183	0	22	0	0
T185	0	18	0	0
T186	0	103	0	0
T187	0	3	0	0
T188	0	3	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2110	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	48	0	0
T80	27303	19	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	16	0	0
T155	0	4	0	0
T162	0	72	0	0
T183	0	25	0	0
T184	0	14	0	0
T185	0	4	0	0
T186	0	114	0	0
T187	0	9	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2123	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	73	0	0
T80	27303	29	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	45	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	7	0	0
T155	0	9	0	0
T162	0	56	0	0
T183	0	25	0	0
T186	0	127	0	0
T187	0	3	0	0
T188	0	2	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2317	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	46	0	0
T80	27303	25	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	6	0	0
T155	0	9	0	0
T162	0	53	0	0
T183	0	16	0	0
T184	0	2	0	0
T185	0	7	0	0
T186	0	165	0	0
T187	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2187	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	41	0	0
T80	27303	32	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	51	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	7	0	0
T155	0	5	0	0
T162	0	62	0	0
T183	0	22	0	0
T184	0	19	0	0
T186	0	140	0	0
T187	0	5	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2079	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	38	0	0
T80	27303	29	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	59	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	10	0	0
T162	0	55	0	0
T183	0	26	0	0
T184	0	10	0	0
T185	0	13	0	0
T186	0	156	0	0
T188	0	3	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2139	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	53	0	0
T80	27303	35	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	8	0	0
T162	0	39	0	0
T183	0	28	0	0
T184	0	11	0	0
T185	0	10	0	0
T186	0	172	0	0
T187	0	13	0	0
T188	0	6	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2090	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	44	0	0
T80	27303	17	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	56	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	8	0	0
T155	0	7	0	0
T162	0	65	0	0
T183	0	20	0	0
T184	0	2	0	0
T185	0	5	0	0
T186	0	161	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2481	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	87	0	0
T80	27303	37	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	43	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	8	0	0
T162	0	52	0	0
T183	0	22	0	0
T184	0	6	0	0
T185	0	13	0	0
T186	0	206	0	0
T188	0	4	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2207	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	55	0	0
T80	27303	32	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	8	0	0
T155	0	6	0	0
T162	0	40	0	0
T183	0	25	0	0
T184	0	1	0	0
T185	0	17	0	0
T186	0	133	0	0
T188	0	3	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2017	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	67	0	0
T80	27303	23	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	51	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T142	0	5	0	0
T155	0	6	0	0
T162	0	57	0	0
T183	0	35	0	0
T185	0	5	0	0
T186	0	132	0	0
T187	0	2	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2271	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	35	0	0
T80	27303	23	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	3	0	0
T155	0	6	0	0
T162	0	62	0	0
T183	0	22	0	0
T184	0	15	0	0
T185	0	3	0	0
T186	0	194	0	0
T187	0	4	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2095	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	34	0	0
T80	27303	36	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	3	0	0
T155	0	5	0	0
T162	0	65	0	0
T183	0	16	0	0
T184	0	10	0	0
T185	0	4	0	0
T186	0	131	0	0
T188	0	14	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2161	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	34	0	0
T80	27303	19	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	6	0	0
T162	0	34	0	0
T183	0	30	0	0
T184	0	13	0	0
T185	0	5	0	0
T186	0	133	0	0
T187	0	8	0	0
T188	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2375	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	59	0	0
T80	27303	48	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	3	0	0
T155	0	9	0	0
T162	0	50	0	0
T183	0	8	0	0
T184	0	6	0	0
T185	0	20	0	0
T186	0	130	0	0
T188	0	11	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2114	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	54	0	0
T80	27303	23	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	30	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	7	0	0
T155	0	12	0	0
T162	0	60	0	0
T183	0	32	0	0
T185	0	13	0	0
T186	0	122	0	0
T188	0	9	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2324	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	32	0	0
T80	27303	28	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	75	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T141	0	2	0	0
T155	0	12	0	0
T162	0	80	0	0
T183	0	22	0	0
T184	0	3	0	0
T185	0	7	0	0
T186	0	123	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22752379	2275	0	0
T7	9534	0	0	0
T60	32171	0	0	0
T66	0	56	0	0
T80	27303	20	0	0
T81	9546	0	0	0
T82	10026	0	0	0
T83	2632	0	0	0
T84	11128	0	0	0
T85	83087	0	0	0
T119	0	46	0	0
T128	20461	0	0	0
T129	18175	0	0	0
T155	0	10	0	0
T162	0	54	0	0
T183	0	25	0	0
T184	0	7	0	0
T186	0	131	0	0
T188	0	6	0	0
T189	0	8	0	0