Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3134218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

603029

1

T1

935

T2

220

T3

305

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3333059	1			T1	8831		T2	528		T3	227
values[0x0]	200436	1			T1	338		T2	47		T3	173
values[0x1]	203752	1			T1	321		T2	68		T3	149

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2147499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1589748

1

T1

3718

T2

326

T3

353

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15160	1			T1	29		T2	5		T14	6
valid_sources[0x01]	12728	1			T1	29		T2	5		T6	5
valid_sources[0x02]	14051	1			T1	46		T15	6		T16	5
valid_sources[0x03]	13004	1			T1	26		T2	8		T6	2
valid_sources[0x04]	11593	1			T1	34		T2	2		T14	3
valid_sources[0x05]	13070	1			T1	41		T2	1		T6	2
valid_sources[0x06]	11487	1			T1	28		T2	4		T6	1
valid_sources[0x07]	18220	1			T1	44		T2	2		T15	6
valid_sources[0x08]	12515	1			T1	29		T2	2		T6	1
valid_sources[0x09]	26909	1			T1	39		T6	2		T15	7
valid_sources[0x0a]	12703	1			T1	30		T2	1		T6	2
valid_sources[0x0b]	12153	1			T1	26		T2	1		T6	1
valid_sources[0x0c]	15432	1			T1	50		T2	3		T6	5
valid_sources[0x0d]	18316	1			T1	36		T6	3		T15	5
valid_sources[0x0e]	11307	1			T1	38		T6	2		T15	12
valid_sources[0x0f]	13577	1			T1	28		T2	9		T6	1
valid_sources[0x10]	18315	1			T1	39		T2	5		T6	1
valid_sources[0x11]	13553	1			T1	26		T2	1		T6	2
valid_sources[0x12]	32962	1			T1	36		T2	1		T6	3
valid_sources[0x13]	13640	1			T1	37		T6	4		T14	4
valid_sources[0x14]	13725	1			T1	50		T2	4		T6	3
valid_sources[0x15]	14622	1			T1	42		T2	3		T15	2
valid_sources[0x16]	13516	1			T1	33		T2	5		T6	1
valid_sources[0x17]	11734	1			T1	38		T2	3		T6	5
valid_sources[0x18]	14341	1			T1	34		T2	2		T6	6
valid_sources[0x19]	11876	1			T1	41		T2	6		T6	1
valid_sources[0x1a]	13255	1			T1	39		T2	5		T6	3
valid_sources[0x1b]	12698	1			T1	38		T2	1		T15	10
valid_sources[0x1c]	12235	1			T1	26		T2	2		T6	8
valid_sources[0x1d]	11994	1			T1	33		T2	1		T14	1
valid_sources[0x1e]	12717	1			T1	45		T2	3		T6	2
valid_sources[0x1f]	12980	1			T1	45		T2	2		T14	4
valid_sources[0x20]	11364	1			T1	33		T2	1		T6	1
valid_sources[0x21]	11611	1			T1	52		T6	2		T15	4
valid_sources[0x22]	153119	1			T1	43		T2	3		T6	1
valid_sources[0x23]	11548	1			T1	41		T2	2		T6	1
valid_sources[0x24]	11979	1			T1	24		T6	2		T15	5
valid_sources[0x25]	13717	1			T1	27		T2	4		T6	2
valid_sources[0x26]	13292	1			T1	33		T6	2		T15	2
valid_sources[0x27]	15635	1			T1	50		T2	4		T6	3
valid_sources[0x28]	11683	1			T1	34		T2	4		T15	6
valid_sources[0x29]	12837	1			T1	22		T2	1		T14	4
valid_sources[0x2a]	11447	1			T1	24		T2	2		T6	1
valid_sources[0x2b]	11655	1			T1	40		T2	2		T6	1
valid_sources[0x2c]	11639	1			T1	39		T2	3		T6	1
valid_sources[0x2d]	15504	1			T1	42		T2	3		T6	8
valid_sources[0x2e]	12260	1			T1	23		T2	8		T14	1
valid_sources[0x2f]	12801	1			T1	47		T2	2		T6	5
valid_sources[0x30]	11072	1			T1	40		T6	3		T14	3
valid_sources[0x31]	12805	1			T1	33		T2	1		T14	1
valid_sources[0x32]	13884	1			T1	41		T2	3		T6	1
valid_sources[0x33]	11182	1			T1	43		T2	2		T6	2
valid_sources[0x34]	11324	1			T1	36		T6	3		T14	7
valid_sources[0x35]	10922	1			T1	32		T2	3		T15	5
valid_sources[0x36]	12187	1			T1	42		T2	1		T6	3
valid_sources[0x37]	11672	1			T1	39		T2	1		T6	3
valid_sources[0x38]	13762	1			T1	39		T2	12		T6	4
valid_sources[0x39]	14298	1			T1	41		T2	7		T6	5
valid_sources[0x3a]	15163	1			T1	47		T2	5		T6	2
valid_sources[0x3b]	13616	1			T1	30		T6	3		T14	5
valid_sources[0x3c]	12709	1			T1	46		T2	4		T6	3
valid_sources[0x3d]	14289	1			T1	50		T6	2		T14	1
valid_sources[0x3e]	11934	1			T1	38		T6	1		T14	1
valid_sources[0x3f]	12198	1			T1	41		T2	1		T14	1
valid_sources[0x40]	15438	1			T1	36		T2	1		T6	4
valid_sources[0x41]	17770	1			T1	39		T15	10		T16	2
valid_sources[0x42]	13978	1			T1	42		T2	1		T6	2
valid_sources[0x43]	13369	1			T1	40		T2	3		T15	2
valid_sources[0x44]	11054	1			T1	48		T2	2		T6	1
valid_sources[0x45]	12877	1			T1	37		T2	1		T6	4
valid_sources[0x46]	14849	1			T1	33		T6	4		T14	1
valid_sources[0x47]	12256	1			T1	35		T2	4		T6	1
valid_sources[0x48]	12092	1			T1	30		T2	3		T14	1
valid_sources[0x49]	11546	1			T1	32		T2	3		T15	4
valid_sources[0x4a]	14521	1			T1	31		T15	1		T16	7
valid_sources[0x4b]	14666	1			T1	38		T2	1		T15	10
valid_sources[0x4c]	15055	1			T1	35		T2	1		T6	2
valid_sources[0x4d]	13087	1			T1	29		T2	4		T6	1
valid_sources[0x4e]	28797	1			T1	36		T2	1		T6	2
valid_sources[0x4f]	14302	1			T1	39		T2	4		T6	2
valid_sources[0x50]	11995	1			T1	40		T2	4		T6	1
valid_sources[0x51]	11628	1			T1	41		T15	5		T16	3
valid_sources[0x52]	18309	1			T1	45		T6	5		T14	2
valid_sources[0x53]	11685	1			T1	33		T2	8		T6	4
valid_sources[0x54]	20864	1			T1	37		T2	2		T6	1
valid_sources[0x55]	11969	1			T1	39		T2	5		T6	5
valid_sources[0x56]	13361	1			T1	28		T4	755		T6	2
valid_sources[0x57]	11246	1			T1	29		T6	2		T14	1
valid_sources[0x58]	11979	1			T1	44		T2	3		T6	2
valid_sources[0x59]	12826	1			T1	42		T15	13		T16	7
valid_sources[0x5a]	14188	1			T1	33		T6	1		T14	3
valid_sources[0x5b]	13127	1			T1	45		T6	3		T14	2
valid_sources[0x5c]	11767	1			T1	36		T2	15		T15	9
valid_sources[0x5d]	11953	1			T1	38		T2	2		T6	1
valid_sources[0x5e]	11943	1			T1	50		T2	4		T6	2
valid_sources[0x5f]	30370	1			T1	47		T2	3		T6	2
valid_sources[0x60]	14457	1			T1	40		T6	4		T15	2
valid_sources[0x61]	11534	1			T1	42		T2	1		T6	3
valid_sources[0x62]	12574	1			T1	32		T6	8		T14	1
valid_sources[0x63]	13618	1			T1	40		T2	2		T15	3
valid_sources[0x64]	14263	1			T1	33		T2	7		T6	2
valid_sources[0x65]	19050	1			T1	35		T2	2		T6	4
valid_sources[0x66]	14955	1			T1	43		T2	2		T6	1
valid_sources[0x67]	12441	1			T1	32		T2	1		T6	3
valid_sources[0x68]	11658	1			T1	58		T2	4		T6	1
valid_sources[0x69]	13307	1			T1	30		T6	9		T15	5
valid_sources[0x6a]	11612	1			T1	32		T6	1		T14	7
valid_sources[0x6b]	11914	1			T1	31		T2	1		T6	5
valid_sources[0x6c]	12335	1			T1	39		T2	4		T6	6
valid_sources[0x6d]	14506	1			T1	30		T2	3		T6	2
valid_sources[0x6e]	11307	1			T1	47		T2	5		T14	7
valid_sources[0x6f]	12246	1			T1	31		T6	1		T14	5
valid_sources[0x70]	13227	1			T1	29		T6	1		T15	4
valid_sources[0x71]	15873	1			T1	40		T6	5		T15	4
valid_sources[0x72]	12003	1			T1	29		T2	3		T14	1
valid_sources[0x73]	12657	1			T1	33		T2	3		T6	6
valid_sources[0x74]	11274	1			T1	39		T2	1		T14	4
valid_sources[0x75]	12204	1			T1	54		T6	3		T15	6
valid_sources[0x76]	25338	1			T1	37		T15	9		T16	6
valid_sources[0x77]	13267	1			T1	41		T2	1		T6	4
valid_sources[0x78]	28856	1			T1	28		T2	3		T6	2
valid_sources[0x79]	11827	1			T1	23		T2	1		T6	6
valid_sources[0x7a]	13529	1			T1	49		T15	7		T16	5
valid_sources[0x7b]	13515	1			T1	45		T2	4		T14	1
valid_sources[0x7c]	16135	1			T1	31		T2	4		T14	3
valid_sources[0x7d]	15976	1			T1	34		T2	7		T15	5
valid_sources[0x7e]	12581	1			T1	30		T2	7		T6	1
valid_sources[0x7f]	14291	1			T1	35		T6	2		T14	1
valid_sources[0x80]	11522	1			T1	47		T2	3		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325104

1

T1

453

T2

177

T3

88

values[0x0]

all_enables

biggest_size

145532

1

T1

251

T2

22

T3

120

values[0x1]

all_enables

biggest_size

132393

1

T1

231

T2

21

T3

97