Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22744105	13969	0	0
attest_sw_binding_0_rd_A	22744105	2303	0	0
attest_sw_binding_1_rd_A	22744105	2403	0	0
attest_sw_binding_2_rd_A	22744105	2284	0	0
attest_sw_binding_3_rd_A	22744105	2176	0	0
attest_sw_binding_4_rd_A	22744105	2402	0	0
attest_sw_binding_5_rd_A	22744105	2272	0	0
attest_sw_binding_6_rd_A	22744105	2302	0	0
attest_sw_binding_7_rd_A	22744105	2249	0	0
intr_enable_rd_A	22744105	3110	0	0
key_version_rd_A	22744105	2188	0	0
max_creator_key_ver_regwen_rd_A	22744105	2351	0	0
max_owner_int_key_ver_regwen_rd_A	22744105	2314	0	0
max_owner_key_ver_regwen_rd_A	22744105	2315	0	0
reseed_interval_regwen_rd_A	22744105	2228	0	0
salt_0_rd_A	22744105	2198	0	0
salt_1_rd_A	22744105	2215	0	0
salt_2_rd_A	22744105	2370	0	0
salt_3_rd_A	22744105	2362	0	0
salt_4_rd_A	22744105	2506	0	0
salt_5_rd_A	22744105	2340	0	0
salt_6_rd_A	22744105	2341	0	0
salt_7_rd_A	22744105	2306	0	0
sealing_sw_binding_0_rd_A	22744105	2336	0	0
sealing_sw_binding_1_rd_A	22744105	2302	0	0
sealing_sw_binding_2_rd_A	22744105	2272	0	0
sealing_sw_binding_3_rd_A	22744105	2202	0	0
sealing_sw_binding_4_rd_A	22744105	2290	0	0
sealing_sw_binding_5_rd_A	22744105	2148	0	0
sealing_sw_binding_6_rd_A	22744105	2250	0	0
sealing_sw_binding_7_rd_A	22744105	2278	0	0
sideload_clear_rd_A	22744105	2363	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	13969	0	0
T28	27814	0	0	0
T29	41980	0	0	0
T30	12420	383	0	0
T53	0	267	0	0
T67	0	720	0	0
T68	6069	0	0	0
T70	0	85	0	0
T85	49876	260	0	0
T86	31701	0	0	0
T87	90294	0	0	0
T107	0	216	0	0
T108	0	59	0	0
T128	0	59	0	0
T129	0	732	0	0
T130	0	24	0	0
T131	12405	0	0	0
T132	3040	0	0	0
T133	14237	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2303	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	70	0	0
T128	0	13	0	0
T130	0	15	0	0
T147	0	20	0	0
T157	0	13	0	0
T181	0	39	0	0
T182	0	28	0	0
T183	0	21	0	0
T184	0	76	0	0
T185	0	10	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2403	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	85	0	0
T128	0	11	0	0
T130	0	23	0	0
T157	0	13	0	0
T175	0	24	0	0
T181	0	78	0	0
T182	0	18	0	0
T183	0	40	0	0
T184	0	82	0	0
T185	0	23	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2284	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	46	0	0
T128	0	24	0	0
T130	0	16	0	0
T157	0	15	0	0
T181	0	43	0	0
T182	0	36	0	0
T183	0	30	0	0
T184	0	55	0	0
T185	0	20	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0
T191	0	1	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2176	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	41	0	0
T128	0	35	0	0
T130	0	22	0	0
T147	0	8	0	0
T157	0	26	0	0
T181	0	69	0	0
T182	0	33	0	0
T183	0	16	0	0
T184	0	48	0	0
T185	0	17	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2402	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	34	0	0
T128	0	53	0	0
T130	0	25	0	0
T147	0	31	0	0
T157	0	17	0	0
T181	0	33	0	0
T182	0	26	0	0
T183	0	50	0	0
T184	0	47	0	0
T185	0	26	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2272	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	48	0	0
T128	0	29	0	0
T130	0	11	0	0
T147	0	14	0	0
T157	0	16	0	0
T181	0	63	0	0
T182	0	30	0	0
T183	0	28	0	0
T184	0	77	0	0
T185	0	31	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2302	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	75	0	0
T128	0	32	0	0
T130	0	7	0	0
T147	0	42	0	0
T157	0	18	0	0
T181	0	41	0	0
T182	0	32	0	0
T183	0	19	0	0
T184	0	38	0	0
T185	0	41	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2249	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	64	0	0
T128	0	37	0	0
T130	0	28	0	0
T147	0	28	0	0
T157	0	13	0	0
T181	0	42	0	0
T182	0	23	0	0
T183	0	19	0	0
T184	0	72	0	0
T185	0	30	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	3110	0	0
T18	4344	0	0	0
T55	0	78	0	0
T58	164736	16	0	0
T61	0	46	0	0
T69	9616	0	0	0
T77	0	50	0	0
T108	0	128	0	0
T128	0	69	0	0
T130	0	9	0	0
T135	217601	0	0	0
T136	11742	0	0	0
T137	3791	0	0	0
T138	2213	0	0	0
T139	18357	0	0	0
T140	3144	0	0	0
T141	6775	0	0	0
T181	0	108	0	0
T188	0	4	0	0
T192	0	46	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2188	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	68	0	0
T128	0	24	0	0
T130	0	16	0	0
T147	0	42	0	0
T157	0	15	0	0
T181	0	52	0	0
T182	0	27	0	0
T183	0	44	0	0
T184	0	80	0	0
T185	0	42	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2351	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	36	0	0
T128	0	59	0	0
T130	0	14	0	0
T147	0	38	0	0
T157	0	8	0	0
T181	0	44	0	0
T182	0	17	0	0
T183	0	37	0	0
T184	0	67	0	0
T185	0	40	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2314	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	54	0	0
T128	0	31	0	0
T130	0	23	0	0
T147	0	22	0	0
T157	0	15	0	0
T181	0	58	0	0
T182	0	29	0	0
T183	0	25	0	0
T184	0	45	0	0
T185	0	26	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2315	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	64	0	0
T128	0	25	0	0
T130	0	19	0	0
T147	0	30	0	0
T157	0	16	0	0
T181	0	31	0	0
T182	0	21	0	0
T183	0	35	0	0
T184	0	54	0	0
T185	0	10	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2228	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	46	0	0
T128	0	44	0	0
T130	0	22	0	0
T147	0	26	0	0
T157	0	25	0	0
T181	0	68	0	0
T182	0	31	0	0
T183	0	16	0	0
T184	0	39	0	0
T185	0	11	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2198	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	67	0	0
T128	0	18	0	0
T130	0	16	0	0
T147	0	19	0	0
T157	0	18	0	0
T181	0	50	0	0
T182	0	29	0	0
T183	0	15	0	0
T184	0	56	0	0
T185	0	24	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2215	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	65	0	0
T128	0	19	0	0
T130	0	16	0	0
T157	0	9	0	0
T181	0	64	0	0
T182	0	35	0	0
T183	0	18	0	0
T184	0	51	0	0
T185	0	25	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0
T193	0	10	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2370	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	71	0	0
T128	0	25	0	0
T130	0	10	0	0
T147	0	20	0	0
T157	0	22	0	0
T181	0	74	0	0
T182	0	35	0	0
T183	0	31	0	0
T184	0	54	0	0
T185	0	35	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2362	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	54	0	0
T128	0	26	0	0
T130	0	24	0	0
T147	0	6	0	0
T157	0	13	0	0
T181	0	53	0	0
T182	0	23	0	0
T183	0	22	0	0
T184	0	59	0	0
T185	0	19	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2506	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	60	0	0
T128	0	58	0	0
T130	0	20	0	0
T147	0	15	0	0
T157	0	11	0	0
T181	0	59	0	0
T182	0	14	0	0
T183	0	38	0	0
T184	0	62	0	0
T185	0	33	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2340	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	49	0	0
T128	0	44	0	0
T130	0	5	0	0
T147	0	29	0	0
T157	0	27	0	0
T181	0	48	0	0
T182	0	22	0	0
T183	0	28	0	0
T184	0	51	0	0
T185	0	20	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2341	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	61	0	0
T128	0	16	0	0
T130	0	27	0	0
T147	0	17	0	0
T157	0	10	0	0
T181	0	52	0	0
T182	0	36	0	0
T183	0	21	0	0
T184	0	39	0	0
T185	0	29	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2306	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	75	0	0
T128	0	21	0	0
T130	0	11	0	0
T147	0	35	0	0
T157	0	12	0	0
T181	0	52	0	0
T182	0	32	0	0
T183	0	22	0	0
T184	0	45	0	0
T185	0	31	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2336	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	64	0	0
T128	0	39	0	0
T130	0	24	0	0
T157	0	25	0	0
T181	0	46	0	0
T182	0	19	0	0
T183	0	25	0	0
T184	0	58	0	0
T185	0	31	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0
T194	0	1	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2302	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	64	0	0
T128	0	36	0	0
T130	0	16	0	0
T147	0	26	0	0
T157	0	12	0	0
T181	0	45	0	0
T182	0	28	0	0
T183	0	28	0	0
T184	0	60	0	0
T185	0	27	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2272	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	65	0	0
T128	0	19	0	0
T130	0	8	0	0
T147	0	34	0	0
T157	0	16	0	0
T181	0	76	0	0
T182	0	25	0	0
T183	0	25	0	0
T184	0	57	0	0
T185	0	33	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2202	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	71	0	0
T128	0	25	0	0
T130	0	13	0	0
T147	0	12	0	0
T157	0	18	0	0
T181	0	40	0	0
T182	0	24	0	0
T183	0	27	0	0
T184	0	89	0	0
T185	0	29	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2290	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	57	0	0
T128	0	12	0	0
T130	0	12	0	0
T157	0	28	0	0
T181	0	76	0	0
T182	0	36	0	0
T183	0	26	0	0
T184	0	40	0	0
T185	0	23	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0
T195	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2148	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	55	0	0
T128	0	27	0	0
T130	0	16	0	0
T147	0	21	0	0
T157	0	19	0	0
T181	0	38	0	0
T182	0	32	0	0
T183	0	38	0	0
T184	0	61	0	0
T185	0	38	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2250	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	76	0	0
T128	0	38	0	0
T130	0	8	0	0
T147	0	20	0	0
T157	0	16	0	0
T181	0	47	0	0
T182	0	29	0	0
T183	0	20	0	0
T184	0	45	0	0
T185	0	20	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2278	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	67	0	0
T128	0	18	0	0
T130	0	2	0	0
T147	0	22	0	0
T157	0	11	0	0
T181	0	72	0	0
T182	0	35	0	0
T183	0	28	0	0
T184	0	54	0	0
T185	0	34	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22744105	2363	0	0
T40	3152	0	0	0
T43	10213	0	0	0
T52	623448	0	0	0
T63	4496	0	0	0
T108	47370	52	0	0
T128	0	53	0	0
T130	0	19	0	0
T147	0	13	0	0
T157	0	22	0	0
T181	0	40	0	0
T182	0	32	0	0
T183	0	19	0	0
T184	0	69	0	0
T185	0	35	0	0
T186	1393	0	0	0
T187	6741	0	0	0
T188	22811	0	0	0
T189	8084	0	0	0
T190	22257	0	0	0