Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4036114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

652619

1

T1

292

T2

402

T3

605

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4250328	1			T1	716		T2	357		T3	2700
values[0x0]	216830	1			T1	112		T2	172		T3	207
values[0x1]	221575	1			T1	129		T2	193		T3	199

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2752071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1936662

1

T1

499

T2

480

T3

1399

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15682	1			T1	2		T2	7		T3	11
valid_sources[0x01]	24065	1			T1	3		T2	1		T3	13
valid_sources[0x02]	16295	1			T1	3		T2	1		T3	14
valid_sources[0x03]	15229	1			T1	3		T2	1		T3	16
valid_sources[0x04]	15018	1			T1	3		T2	5		T3	17
valid_sources[0x05]	37289	1			T1	1		T2	2		T3	11
valid_sources[0x06]	17652	1			T1	4		T2	2		T3	7
valid_sources[0x07]	19128	1			T1	3		T2	2		T3	2
valid_sources[0x08]	17089	1			T1	5		T2	2		T3	9
valid_sources[0x09]	18786	1			T1	2		T2	2		T3	8
valid_sources[0x0a]	18428	1			T1	5		T3	14		T17	5
valid_sources[0x0b]	18171	1			T2	7		T3	7		T13	4
valid_sources[0x0c]	17220	1			T1	2		T2	5		T3	12
valid_sources[0x0d]	15402	1			T1	5		T2	2		T3	13
valid_sources[0x0e]	16505	1			T1	3		T2	2		T3	11
valid_sources[0x0f]	16233	1			T1	3		T2	2		T3	9
valid_sources[0x10]	17251	1			T1	4		T2	4		T3	10
valid_sources[0x11]	16437	1			T1	1		T2	5		T3	10
valid_sources[0x12]	16855	1			T1	7		T2	4		T3	15
valid_sources[0x13]	22206	1			T1	2		T2	1		T3	12
valid_sources[0x14]	15691	1			T1	3		T2	3		T3	9
valid_sources[0x15]	15248	1			T1	8		T2	4		T3	10
valid_sources[0x16]	15111	1			T1	3		T2	4		T3	9
valid_sources[0x17]	16076	1			T1	6		T2	3		T3	12
valid_sources[0x18]	29247	1			T1	5		T2	2		T3	22
valid_sources[0x19]	17307	1			T1	9		T2	2		T3	10
valid_sources[0x1a]	16590	1			T1	5		T2	10		T3	11
valid_sources[0x1b]	15792	1			T1	1		T2	1		T3	19
valid_sources[0x1c]	37122	1			T1	3		T2	4		T3	11
valid_sources[0x1d]	17327	1			T1	2		T3	12		T14	9
valid_sources[0x1e]	18050	1			T1	1		T2	2		T3	9
valid_sources[0x1f]	22032	1			T1	4		T3	14		T14	3
valid_sources[0x20]	15852	1			T1	7		T2	2		T3	13
valid_sources[0x21]	16494	1			T1	4		T2	3		T3	11
valid_sources[0x22]	16573	1			T1	1		T2	6		T3	15
valid_sources[0x23]	15303	1			T1	6		T2	5		T3	9
valid_sources[0x24]	15642	1			T1	5		T3	14		T17	4
valid_sources[0x25]	17421	1			T1	3		T2	1		T3	16
valid_sources[0x26]	15039	1			T1	2		T3	13		T18	3
valid_sources[0x27]	18966	1			T1	2		T2	3		T3	12
valid_sources[0x28]	20507	1			T1	4		T2	2		T3	17
valid_sources[0x29]	16932	1			T1	8		T2	4		T3	11
valid_sources[0x2a]	18021	1			T1	7		T2	1		T3	9
valid_sources[0x2b]	15151	1			T1	5		T2	5		T3	10
valid_sources[0x2c]	15351	1			T1	5		T2	7		T3	10
valid_sources[0x2d]	15446	1			T1	5		T2	1		T3	14
valid_sources[0x2e]	18224	1			T1	2		T2	2		T3	21
valid_sources[0x2f]	14840	1			T1	7		T2	6		T3	15
valid_sources[0x30]	18494	1			T1	1		T2	6		T3	12
valid_sources[0x31]	14246	1			T1	3		T2	2		T3	14
valid_sources[0x32]	14675	1			T1	5		T2	3		T3	18
valid_sources[0x33]	18856	1			T1	4		T2	2		T3	13
valid_sources[0x34]	15153	1			T1	4		T2	4		T3	14
valid_sources[0x35]	14365	1			T2	4		T3	15		T13	1
valid_sources[0x36]	15154	1			T1	6		T2	1		T3	10
valid_sources[0x37]	15896	1			T1	8		T2	2		T3	13
valid_sources[0x38]	15562	1			T1	2		T2	3		T3	10
valid_sources[0x39]	15997	1			T1	4		T2	5		T3	9
valid_sources[0x3a]	15791	1			T1	2		T2	7		T3	15
valid_sources[0x3b]	15685	1			T1	1		T2	1		T3	10
valid_sources[0x3c]	20459	1			T1	7		T2	9		T3	9
valid_sources[0x3d]	14483	1			T1	2		T2	1		T3	8
valid_sources[0x3e]	16221	1			T1	7		T2	1		T3	13
valid_sources[0x3f]	17607	1			T1	5		T2	7		T3	7
valid_sources[0x40]	15622	1			T1	2		T2	2		T3	9
valid_sources[0x41]	26446	1			T1	3		T2	3		T3	7
valid_sources[0x42]	15458	1			T1	6		T3	5		T13	2
valid_sources[0x43]	26957	1			T1	4		T2	1		T3	13
valid_sources[0x44]	32351	1			T1	1		T2	2		T3	20
valid_sources[0x45]	14723	1			T1	2		T2	1		T3	11
valid_sources[0x46]	61361	1			T1	5		T2	4		T3	15
valid_sources[0x47]	15961	1			T1	1		T2	3		T3	17
valid_sources[0x48]	16003	1			T1	2		T3	16		T13	5
valid_sources[0x49]	18962	1			T1	3		T2	1		T3	13
valid_sources[0x4a]	21545	1			T1	4		T2	2		T3	14
valid_sources[0x4b]	15679	1			T1	3		T2	3		T3	8
valid_sources[0x4c]	16280	1			T1	1		T2	3		T3	15
valid_sources[0x4d]	15668	1			T1	3		T2	5		T3	13
valid_sources[0x4e]	15459	1			T1	2		T2	4		T3	10
valid_sources[0x4f]	15507	1			T1	5		T2	4		T3	9
valid_sources[0x50]	15582	1			T1	2		T2	3		T3	4
valid_sources[0x51]	16293	1			T1	2		T2	1		T3	8
valid_sources[0x52]	15012	1			T3	18		T17	6		T18	3
valid_sources[0x53]	15056	1			T2	2		T3	8		T13	2
valid_sources[0x54]	15471	1			T1	2		T2	9		T3	23
valid_sources[0x55]	15689	1			T1	3		T2	7		T3	5
valid_sources[0x56]	14943	1			T1	1		T2	2		T3	7
valid_sources[0x57]	15920	1			T1	1		T2	8		T3	8
valid_sources[0x58]	16694	1			T1	3		T2	1		T3	12
valid_sources[0x59]	17318	1			T1	4		T2	2		T3	12
valid_sources[0x5a]	21241	1			T1	2		T2	2		T3	15
valid_sources[0x5b]	16372	1			T1	2		T2	4		T3	11
valid_sources[0x5c]	15393	1			T1	2		T2	3		T3	9
valid_sources[0x5d]	18828	1			T2	4		T3	15		T14	6
valid_sources[0x5e]	15088	1			T1	8		T2	1		T3	13
valid_sources[0x5f]	16813	1			T1	4		T2	1		T3	9
valid_sources[0x60]	16918	1			T1	3		T2	3		T3	11
valid_sources[0x61]	16652	1			T1	4		T3	15		T13	7
valid_sources[0x62]	17079	1			T1	6		T2	5		T3	22
valid_sources[0x63]	17232	1			T1	6		T2	4		T3	6
valid_sources[0x64]	16008	1			T1	8		T2	6		T3	15
valid_sources[0x65]	27529	1			T1	1		T2	5		T3	6
valid_sources[0x66]	14922	1			T1	5		T2	6		T3	14
valid_sources[0x67]	22217	1			T1	8		T2	2		T3	11
valid_sources[0x68]	17815	1			T1	3		T2	4		T3	13
valid_sources[0x69]	15579	1			T1	4		T2	3		T3	18
valid_sources[0x6a]	14974	1			T1	4		T2	2		T3	10
valid_sources[0x6b]	15055	1			T1	3		T2	1		T3	12
valid_sources[0x6c]	15375	1			T1	3		T2	4		T3	14
valid_sources[0x6d]	21924	1			T1	5		T2	2		T3	6
valid_sources[0x6e]	16537	1			T1	5		T2	1		T3	15
valid_sources[0x6f]	15232	1			T1	3		T2	3		T3	8
valid_sources[0x70]	19637	1			T1	3		T2	6		T3	19
valid_sources[0x71]	20859	1			T1	7		T3	13		T14	3
valid_sources[0x72]	14945	1			T1	5		T2	4		T3	15
valid_sources[0x73]	15732	1			T1	2		T2	3		T3	7
valid_sources[0x74]	15487	1			T1	11		T2	3		T3	9
valid_sources[0x75]	16199	1			T1	3		T2	6		T3	10
valid_sources[0x76]	15675	1			T1	6		T2	2		T3	11
valid_sources[0x77]	15818	1			T1	5		T2	3		T3	11
valid_sources[0x78]	15950	1			T1	3		T3	14		T14	7
valid_sources[0x79]	167197	1			T1	2		T2	4		T3	5
valid_sources[0x7a]	17258	1			T2	2		T3	11		T14	1
valid_sources[0x7b]	16688	1			T1	5		T2	3		T3	5
valid_sources[0x7c]	15221	1			T1	1		T2	4		T3	10
valid_sources[0x7d]	15730	1			T1	4		T2	3		T3	12
valid_sources[0x7e]	16667	1			T1	2		T3	12		T13	4
valid_sources[0x7f]	15062	1			T1	6		T2	1		T3	9
valid_sources[0x80]	16670	1			T1	3		T2	2		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

353299

1

T1

125

T2

150

T3

325

values[0x0]

all_enables

biggest_size

157092

1

T1

82

T2

123

T3

148

values[0x1]

all_enables

biggest_size

142228

1

T1

85

T2

129

T3

132