Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
28483356 |
28318487 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
28483356 |
28318487 |
0 |
0 |
T1 |
3464 |
3389 |
0 |
0 |
T2 |
7574 |
7518 |
0 |
0 |
T3 |
14448 |
14314 |
0 |
0 |
T12 |
846 |
769 |
0 |
0 |
T13 |
7340 |
7189 |
0 |
0 |
T14 |
3173 |
3078 |
0 |
0 |
T15 |
5246 |
5165 |
0 |
0 |
T16 |
3657 |
3605 |
0 |
0 |
T17 |
8002 |
7930 |
0 |
0 |
T18 |
3393 |
3293 |
0 |
0 |