Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.83 96.00 97.27 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 30091134 23104 0 0
attest_sw_binding_0_rd_A 30091134 2924 0 0
attest_sw_binding_1_rd_A 30091134 2879 0 0
attest_sw_binding_2_rd_A 30091134 3029 0 0
attest_sw_binding_3_rd_A 30091134 2989 0 0
attest_sw_binding_4_rd_A 30091134 2864 0 0
attest_sw_binding_5_rd_A 30091134 3000 0 0
attest_sw_binding_6_rd_A 30091134 3034 0 0
attest_sw_binding_7_rd_A 30091134 2951 0 0
intr_enable_rd_A 30091134 3823 0 0
key_version_rd_A 30091134 3026 0 0
max_creator_key_ver_regwen_rd_A 30091134 2953 0 0
max_owner_int_key_ver_regwen_rd_A 30091134 2802 0 0
max_owner_key_ver_regwen_rd_A 30091134 2729 0 0
reseed_interval_regwen_rd_A 30091134 2988 0 0
salt_0_rd_A 30091134 2981 0 0
salt_1_rd_A 30091134 2968 0 0
salt_2_rd_A 30091134 3024 0 0
salt_3_rd_A 30091134 2911 0 0
salt_4_rd_A 30091134 2821 0 0
salt_5_rd_A 30091134 2918 0 0
salt_6_rd_A 30091134 3045 0 0
salt_7_rd_A 30091134 2958 0 0
sealing_sw_binding_0_rd_A 30091134 2881 0 0
sealing_sw_binding_1_rd_A 30091134 2987 0 0
sealing_sw_binding_2_rd_A 30091134 2791 0 0
sealing_sw_binding_3_rd_A 30091134 2950 0 0
sealing_sw_binding_4_rd_A 30091134 3142 0 0
sealing_sw_binding_5_rd_A 30091134 2819 0 0
sealing_sw_binding_6_rd_A 30091134 2788 0 0
sealing_sw_binding_7_rd_A 30091134 2840 0 0
sideload_clear_rd_A 30091134 2903 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 23104 0 0
T5 747184 0 0 0
T21 4270 0 0 0
T43 30790 28 0 0
T47 3373 0 0 0
T51 708055 0 0 0
T57 0 26 0 0
T64 0 551 0 0
T72 4000 0 0 0
T73 1303 0 0 0
T74 34401 0 0 0
T75 17722 0 0 0
T76 13653 0 0 0
T104 0 1158 0 0
T111 0 1084 0 0
T112 0 656 0 0
T113 0 79 0 0
T114 0 1151 0 0
T115 0 555 0 0
T116 0 206 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2924 0 0
T57 30101 9 0 0
T105 0 7 0 0
T121 4115 0 0 0
T144 0 15 0 0
T161 0 30 0 0
T168 0 28 0 0
T169 0 42 0 0
T170 0 18 0 0
T171 0 16 0 0
T172 0 49 0 0
T173 0 4 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2879 0 0
T57 30101 15 0 0
T105 0 9 0 0
T121 4115 0 0 0
T144 0 26 0 0
T161 0 36 0 0
T168 0 29 0 0
T169 0 24 0 0
T170 0 26 0 0
T171 0 37 0 0
T172 0 41 0 0
T173 0 8 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3029 0 0
T57 30101 18 0 0
T105 0 3 0 0
T121 4115 0 0 0
T144 0 29 0 0
T161 0 21 0 0
T168 0 21 0 0
T169 0 14 0 0
T170 0 43 0 0
T171 0 24 0 0
T172 0 29 0 0
T173 0 5 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2989 0 0
T57 30101 16 0 0
T105 0 18 0 0
T121 4115 0 0 0
T144 0 17 0 0
T161 0 32 0 0
T168 0 35 0 0
T169 0 46 0 0
T170 0 32 0 0
T171 0 34 0 0
T172 0 33 0 0
T173 0 3 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2864 0 0
T57 30101 14 0 0
T105 0 21 0 0
T121 4115 0 0 0
T144 0 16 0 0
T161 0 20 0 0
T168 0 30 0 0
T169 0 19 0 0
T170 0 22 0 0
T171 0 28 0 0
T172 0 30 0 0
T173 0 3 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3000 0 0
T57 30101 13 0 0
T105 0 11 0 0
T121 4115 0 0 0
T144 0 20 0 0
T161 0 21 0 0
T168 0 35 0 0
T169 0 15 0 0
T170 0 43 0 0
T171 0 17 0 0
T172 0 26 0 0
T173 0 3 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3034 0 0
T57 30101 13 0 0
T105 0 3 0 0
T121 4115 0 0 0
T144 0 31 0 0
T161 0 29 0 0
T168 0 28 0 0
T169 0 16 0 0
T170 0 17 0 0
T171 0 36 0 0
T172 0 45 0 0
T173 0 2 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2951 0 0
T57 30101 25 0 0
T105 0 9 0 0
T121 4115 0 0 0
T144 0 26 0 0
T161 0 25 0 0
T168 0 28 0 0
T169 0 37 0 0
T170 0 25 0 0
T171 0 25 0 0
T172 0 22 0 0
T173 0 7 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3823 0 0
T5 747184 0 0 0
T21 4270 0 0 0
T43 30790 0 0 0
T46 90351 16 0 0
T51 708055 0 0 0
T57 0 10 0 0
T62 0 15 0 0
T70 0 43 0 0
T72 4000 0 0 0
T73 1303 0 0 0
T74 34401 0 0 0
T75 17722 0 0 0
T76 13653 0 0 0
T168 0 27 0 0
T169 0 45 0 0
T182 0 63 0 0
T183 0 54 0 0
T184 0 67 0 0
T185 0 29 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3026 0 0
T57 30101 8 0 0
T105 0 4 0 0
T121 4115 0 0 0
T144 0 15 0 0
T161 0 23 0 0
T168 0 8 0 0
T169 0 39 0 0
T170 0 29 0 0
T171 0 47 0 0
T172 0 44 0 0
T173 0 5 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2953 0 0
T57 30101 28 0 0
T105 0 13 0 0
T121 4115 0 0 0
T144 0 23 0 0
T161 0 26 0 0
T168 0 37 0 0
T169 0 14 0 0
T170 0 38 0 0
T171 0 29 0 0
T172 0 44 0 0
T173 0 12 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2802 0 0
T57 30101 11 0 0
T105 0 5 0 0
T121 4115 0 0 0
T144 0 12 0 0
T161 0 26 0 0
T168 0 22 0 0
T169 0 25 0 0
T170 0 25 0 0
T171 0 20 0 0
T172 0 31 0 0
T173 0 6 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2729 0 0
T57 30101 9 0 0
T105 0 4 0 0
T121 4115 0 0 0
T144 0 6 0 0
T161 0 31 0 0
T168 0 30 0 0
T169 0 17 0 0
T170 0 36 0 0
T171 0 32 0 0
T172 0 45 0 0
T173 0 13 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2988 0 0
T57 30101 26 0 0
T105 0 14 0 0
T121 4115 0 0 0
T144 0 15 0 0
T161 0 27 0 0
T168 0 26 0 0
T169 0 30 0 0
T170 0 8 0 0
T171 0 31 0 0
T172 0 41 0 0
T173 0 6 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2981 0 0
T57 30101 13 0 0
T105 0 10 0 0
T121 4115 0 0 0
T144 0 23 0 0
T161 0 29 0 0
T168 0 37 0 0
T169 0 30 0 0
T170 0 21 0 0
T171 0 46 0 0
T172 0 67 0 0
T173 0 4 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2968 0 0
T57 30101 18 0 0
T105 0 19 0 0
T121 4115 0 0 0
T144 0 2 0 0
T161 0 27 0 0
T168 0 37 0 0
T169 0 32 0 0
T170 0 31 0 0
T171 0 21 0 0
T172 0 48 0 0
T173 0 7 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3024 0 0
T57 30101 10 0 0
T105 0 14 0 0
T121 4115 0 0 0
T144 0 17 0 0
T161 0 16 0 0
T168 0 25 0 0
T169 0 39 0 0
T170 0 40 0 0
T171 0 40 0 0
T172 0 43 0 0
T173 0 4 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2911 0 0
T57 30101 1 0 0
T105 0 11 0 0
T121 4115 0 0 0
T144 0 26 0 0
T161 0 16 0 0
T168 0 21 0 0
T169 0 18 0 0
T170 0 44 0 0
T171 0 25 0 0
T172 0 38 0 0
T173 0 6 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2821 0 0
T57 30101 9 0 0
T105 0 11 0 0
T121 4115 0 0 0
T144 0 16 0 0
T161 0 20 0 0
T168 0 36 0 0
T169 0 13 0 0
T170 0 22 0 0
T171 0 44 0 0
T172 0 26 0 0
T173 0 6 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2918 0 0
T57 30101 17 0 0
T105 0 2 0 0
T121 4115 0 0 0
T144 0 7 0 0
T161 0 3 0 0
T168 0 41 0 0
T169 0 35 0 0
T170 0 15 0 0
T171 0 32 0 0
T172 0 27 0 0
T173 0 20 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3045 0 0
T57 30101 18 0 0
T105 0 16 0 0
T121 4115 0 0 0
T144 0 26 0 0
T161 0 4 0 0
T168 0 39 0 0
T169 0 21 0 0
T170 0 35 0 0
T171 0 40 0 0
T172 0 40 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0
T186 0 2 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2958 0 0
T57 30101 17 0 0
T105 0 29 0 0
T121 4115 0 0 0
T144 0 32 0 0
T161 0 35 0 0
T168 0 29 0 0
T169 0 27 0 0
T170 0 54 0 0
T171 0 32 0 0
T172 0 43 0 0
T173 0 3 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2881 0 0
T57 30101 2 0 0
T105 0 6 0 0
T121 4115 0 0 0
T144 0 24 0 0
T161 0 7 0 0
T168 0 23 0 0
T169 0 18 0 0
T170 0 31 0 0
T171 0 16 0 0
T172 0 23 0 0
T173 0 11 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2987 0 0
T57 30101 9 0 0
T105 0 9 0 0
T121 4115 0 0 0
T161 0 18 0 0
T168 0 29 0 0
T169 0 22 0 0
T170 0 38 0 0
T171 0 41 0 0
T172 0 40 0 0
T173 0 10 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0
T187 0 149 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2791 0 0
T57 30101 36 0 0
T105 0 10 0 0
T121 4115 0 0 0
T144 0 12 0 0
T161 0 9 0 0
T168 0 48 0 0
T169 0 22 0 0
T170 0 18 0 0
T171 0 16 0 0
T172 0 28 0 0
T173 0 2 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2950 0 0
T57 30101 18 0 0
T105 0 5 0 0
T121 4115 0 0 0
T144 0 14 0 0
T161 0 10 0 0
T168 0 42 0 0
T169 0 20 0 0
T170 0 24 0 0
T171 0 47 0 0
T172 0 37 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0
T187 0 111 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 3142 0 0
T57 30101 10 0 0
T105 0 19 0 0
T121 4115 0 0 0
T144 0 28 0 0
T161 0 30 0 0
T168 0 16 0 0
T169 0 21 0 0
T170 0 20 0 0
T171 0 20 0 0
T172 0 37 0 0
T173 0 5 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2819 0 0
T57 30101 14 0 0
T105 0 5 0 0
T121 4115 0 0 0
T144 0 19 0 0
T161 0 19 0 0
T168 0 31 0 0
T169 0 32 0 0
T170 0 11 0 0
T171 0 24 0 0
T172 0 39 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0
T187 0 121 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2788 0 0
T57 30101 11 0 0
T105 0 13 0 0
T121 4115 0 0 0
T144 0 21 0 0
T161 0 18 0 0
T168 0 39 0 0
T169 0 24 0 0
T170 0 28 0 0
T171 0 48 0 0
T172 0 40 0 0
T173 0 10 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2840 0 0
T57 30101 9 0 0
T105 0 6 0 0
T121 4115 0 0 0
T144 0 10 0 0
T161 0 23 0 0
T168 0 27 0 0
T169 0 22 0 0
T170 0 9 0 0
T171 0 21 0 0
T172 0 19 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0
T188 0 4 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30091134 2903 0 0
T57 30101 35 0 0
T105 0 8 0 0
T121 4115 0 0 0
T144 0 19 0 0
T161 0 35 0 0
T168 0 35 0 0
T169 0 24 0 0
T170 0 25 0 0
T171 0 44 0 0
T172 0 26 0 0
T173 0 35 0 0
T174 5348 0 0 0
T175 8810 0 0 0
T176 21999 0 0 0
T177 30272 0 0 0
T178 21336 0 0 0
T179 4805 0 0 0
T180 16241 0 0 0
T181 3250 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%