Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2703912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

624456

1

T1

124

T2

2618

T3

2812

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2912377	1			T1	350		T2	3034		T3	5693
values[0x0]	206518	1			T1	35		T2	659		T3	869
values[0x1]	209473	1			T1	23		T2	764		T3	875

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1861963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1466405

1

T1

200

T2

3006

T3

3996

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10617	1			T1	3		T2	137		T3	28
valid_sources[0x01]	15036	1			T2	3		T3	32		T11	39
valid_sources[0x02]	11611	1			T1	2		T3	27		T11	6
valid_sources[0x03]	12040	1			T1	1		T2	6		T3	34
valid_sources[0x04]	12767	1			T1	2		T3	22		T11	34
valid_sources[0x05]	13796	1			T1	3		T2	171		T3	31
valid_sources[0x06]	10575	1			T1	1		T2	23		T3	27
valid_sources[0x07]	10145	1			T1	3		T3	29		T11	21
valid_sources[0x08]	9999	1			T1	2		T2	151		T3	21
valid_sources[0x09]	15519	1			T1	2		T2	16		T3	33
valid_sources[0x0a]	12168	1			T1	2		T3	18		T11	28
valid_sources[0x0b]	11609	1			T1	5		T3	17		T11	42
valid_sources[0x0c]	12582	1			T1	4		T3	28		T11	21
valid_sources[0x0d]	10177	1			T1	1		T2	27		T3	24
valid_sources[0x0e]	10190	1			T1	2		T2	14		T3	29
valid_sources[0x0f]	12460	1			T3	23		T11	37		T13	5
valid_sources[0x10]	10905	1			T2	14		T3	24		T11	17
valid_sources[0x11]	14861	1			T1	4		T2	12		T3	38
valid_sources[0x12]	9982	1			T2	24		T3	29		T11	35
valid_sources[0x13]	10478	1			T1	1		T2	15		T3	26
valid_sources[0x14]	10936	1			T1	1		T3	26		T11	24
valid_sources[0x15]	10170	1			T1	6		T2	8		T3	26
valid_sources[0x16]	11578	1			T1	1		T3	25		T11	21
valid_sources[0x17]	13061	1			T1	1		T2	6		T3	30
valid_sources[0x18]	12459	1			T1	2		T3	28		T11	31
valid_sources[0x19]	11025	1			T1	3		T3	31		T11	19
valid_sources[0x1a]	10634	1			T1	2		T2	4		T3	13
valid_sources[0x1b]	10958	1			T1	1		T3	31		T11	89
valid_sources[0x1c]	13498	1			T1	3		T2	4		T3	28
valid_sources[0x1d]	9590	1			T1	2		T2	23		T3	27
valid_sources[0x1e]	9776	1			T1	2		T2	43		T3	23
valid_sources[0x1f]	10422	1			T1	1		T2	21		T3	22
valid_sources[0x20]	30335	1			T3	26		T11	31		T15	12
valid_sources[0x21]	10632	1			T2	29		T3	37		T11	31
valid_sources[0x22]	9992	1			T1	1		T3	33		T11	12
valid_sources[0x23]	11768	1			T1	1		T3	33		T11	34
valid_sources[0x24]	12640	1			T1	1		T2	33		T3	25
valid_sources[0x25]	23073	1			T2	39		T3	28		T11	38
valid_sources[0x26]	11533	1			T1	1		T3	32		T11	36
valid_sources[0x27]	10201	1			T1	4		T2	37		T3	23
valid_sources[0x28]	9989	1			T1	1		T3	32		T11	12
valid_sources[0x29]	10306	1			T1	1		T3	29		T11	25
valid_sources[0x2a]	10783	1			T1	1		T2	11		T3	29
valid_sources[0x2b]	9879	1			T1	1		T3	28		T11	21
valid_sources[0x2c]	11931	1			T1	1		T2	97		T3	18
valid_sources[0x2d]	10667	1			T1	1		T2	75		T3	22
valid_sources[0x2e]	10382	1			T3	36		T11	22		T13	3
valid_sources[0x2f]	10832	1			T1	3		T2	12		T3	21
valid_sources[0x30]	10649	1			T1	3		T2	2		T3	31
valid_sources[0x31]	11692	1			T2	19		T3	35		T11	39
valid_sources[0x32]	13395	1			T1	1		T3	36		T11	29
valid_sources[0x33]	10049	1			T1	1		T3	26		T11	29
valid_sources[0x34]	10462	1			T3	40		T11	17		T13	4
valid_sources[0x35]	9878	1			T1	2		T2	4		T3	32
valid_sources[0x36]	12871	1			T3	42		T11	37		T13	4
valid_sources[0x37]	11596	1			T1	1		T3	24		T11	44
valid_sources[0x38]	21144	1			T1	2		T3	34		T11	18
valid_sources[0x39]	12492	1			T1	5		T2	23		T3	39
valid_sources[0x3a]	11078	1			T1	1		T3	31		T11	24
valid_sources[0x3b]	11091	1			T3	20		T11	38		T13	2
valid_sources[0x3c]	17347	1			T1	1		T2	43		T3	13
valid_sources[0x3d]	11242	1			T1	3		T2	25		T3	28
valid_sources[0x3e]	9548	1			T3	36		T11	37		T13	5
valid_sources[0x3f]	10549	1			T1	2		T2	22		T3	28
valid_sources[0x40]	11562	1			T1	1		T2	6		T3	26
valid_sources[0x41]	51019	1			T1	1		T2	34		T3	29
valid_sources[0x42]	9950	1			T1	3		T2	12		T3	20
valid_sources[0x43]	11607	1			T1	1		T2	83		T3	48
valid_sources[0x44]	12441	1			T1	2		T3	33		T11	40
valid_sources[0x45]	11027	1			T1	2		T2	23		T3	19
valid_sources[0x46]	14281	1			T2	1		T3	28		T11	49
valid_sources[0x47]	14433	1			T1	2		T2	8		T3	27
valid_sources[0x48]	10447	1			T3	26		T11	16		T13	2
valid_sources[0x49]	48075	1			T2	1		T3	18		T11	28
valid_sources[0x4a]	11143	1			T1	2		T3	38		T11	30
valid_sources[0x4b]	11084	1			T1	2		T3	24		T11	10
valid_sources[0x4c]	10193	1			T1	4		T2	3		T3	33
valid_sources[0x4d]	11326	1			T1	2		T2	7		T3	24
valid_sources[0x4e]	10766	1			T2	16		T3	33		T11	22
valid_sources[0x4f]	10294	1			T1	1		T2	20		T3	30
valid_sources[0x50]	10208	1			T1	1		T2	21		T3	18
valid_sources[0x51]	15145	1			T1	2		T3	30		T11	10
valid_sources[0x52]	20600	1			T1	1		T3	22		T11	35
valid_sources[0x53]	10657	1			T1	1		T2	15		T3	21
valid_sources[0x54]	10558	1			T1	1		T2	17		T3	31
valid_sources[0x55]	17239	1			T1	1		T2	11		T3	27
valid_sources[0x56]	12788	1			T1	5		T2	3		T3	29
valid_sources[0x57]	10858	1			T1	3		T3	22		T11	31
valid_sources[0x58]	10505	1			T1	3		T3	39		T11	26
valid_sources[0x59]	10555	1			T3	31		T11	31		T13	2
valid_sources[0x5a]	11867	1			T2	5		T3	20		T11	71
valid_sources[0x5b]	26691	1			T1	1		T2	2		T3	20
valid_sources[0x5c]	14587	1			T1	2		T3	24		T11	40
valid_sources[0x5d]	10832	1			T2	17		T3	29		T11	27
valid_sources[0x5e]	11047	1			T1	1		T2	22		T3	45
valid_sources[0x5f]	11216	1			T1	1		T2	41		T3	35
valid_sources[0x60]	15530	1			T1	1		T2	64		T3	29
valid_sources[0x61]	11295	1			T2	27		T3	39		T11	45
valid_sources[0x62]	10195	1			T1	7		T3	33		T11	13
valid_sources[0x63]	10346	1			T1	1		T2	12		T3	31
valid_sources[0x64]	9541	1			T1	1		T2	17		T3	23
valid_sources[0x65]	10469	1			T1	1		T2	80		T3	35
valid_sources[0x66]	10514	1			T1	1		T2	28		T3	29
valid_sources[0x67]	10867	1			T2	80		T3	35		T11	31
valid_sources[0x68]	15752	1			T1	1		T2	22		T3	22
valid_sources[0x69]	11244	1			T1	1		T3	27		T11	37
valid_sources[0x6a]	11755	1			T1	1		T3	21		T11	6
valid_sources[0x6b]	10360	1			T1	3		T2	18		T3	40
valid_sources[0x6c]	10351	1			T1	2		T2	7		T3	25
valid_sources[0x6d]	11318	1			T1	1		T2	26		T3	23
valid_sources[0x6e]	13082	1			T1	4		T2	24		T3	35
valid_sources[0x6f]	9845	1			T1	1		T2	3		T3	31
valid_sources[0x70]	10317	1			T1	1		T2	17		T3	37
valid_sources[0x71]	11012	1			T1	1		T3	25		T11	11
valid_sources[0x72]	10482	1			T1	3		T3	20		T11	26
valid_sources[0x73]	10488	1			T1	2		T2	23		T3	32
valid_sources[0x74]	10926	1			T1	2		T2	5		T3	30
valid_sources[0x75]	11038	1			T3	35		T11	44		T13	4
valid_sources[0x76]	10159	1			T1	4		T3	22		T11	44
valid_sources[0x77]	10257	1			T1	4		T2	11		T3	34
valid_sources[0x78]	15402	1			T1	2		T2	42		T3	26
valid_sources[0x79]	9864	1			T1	1		T2	26		T3	25
valid_sources[0x7a]	13746	1			T1	1		T2	15		T3	33
valid_sources[0x7b]	10382	1			T1	1		T3	33		T11	26
valid_sources[0x7c]	10074	1			T1	4		T2	65		T3	36
valid_sources[0x7d]	10503	1			T1	3		T2	8		T3	37
valid_sources[0x7e]	11092	1			T1	5		T2	1		T3	32
valid_sources[0x7f]	11748	1			T1	2		T3	31		T11	32
valid_sources[0x80]	10390	1			T1	2		T2	39		T3	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

341759

1

T1

105

T2

1541

T3

1893

values[0x0]

all_enables

biggest_size

148875

1

T1

14

T2

529

T3

520

values[0x1]

all_enables

biggest_size

133822

1

T1

5

T2

548

T3

399