Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21758594 |
21608985 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21758594 |
21608985 |
0 |
0 |
T1 |
2397 |
2340 |
0 |
0 |
T2 |
34834 |
34265 |
0 |
0 |
T3 |
72661 |
71332 |
0 |
0 |
T4 |
76622 |
75180 |
0 |
0 |
T11 |
105574 |
105507 |
0 |
0 |
T12 |
3973 |
3876 |
0 |
0 |
T13 |
6242 |
6189 |
0 |
0 |
T14 |
17504 |
17424 |
0 |
0 |
T15 |
30015 |
29953 |
0 |
0 |
T16 |
7147 |
7010 |
0 |
0 |