Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 96.58 96.58
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 96.58 96.58
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 96.58 96.58
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 97.26 97.26
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 97.95 97.95
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 99.32 99.32


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.26


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.26


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.95 97.95


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.95 97.95


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.32 99.32


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.32 99.32


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.80 100.00 98.11 100.00 100.00 90.91 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 292 292 100.00
Total Bits 0->1 146 146 100.00
Total Bits 1->0 146 146 100.00

Ports 4 4 100.00
Port Bits 292 292 100.00
Port Bits 0->1 146 146 100.00
Port Bits 1->0 146 146 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Yes Yes T61,T154,T155 Yes T61,T154,T155 OUTPUT
err_o[1:0] Yes Yes T61,T154,T155 Yes T61,T154,T155 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[3:0] No No No OUTPUT
syndrome_o[5:4] Yes Yes T157 Yes T157 OUTPUT
syndrome_o[6] No No No OUTPUT
syndrome_o[7] Yes Yes T157 Yes T157 OUTPUT
err_o[0] Yes Yes *T157 Yes T157 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T158 Yes T158 OUTPUT
syndrome_o[1] No No No OUTPUT
syndrome_o[2] Yes Yes *T158 Yes T158 OUTPUT
syndrome_o[4:3] No No No OUTPUT
syndrome_o[5] Yes Yes *T158 Yes T158 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T158 Yes T158 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T2,T3,T11 Yes T2,T3,T11 INPUT
data_o[63:0] Yes Yes T2,T3,T11 Yes T2,T3,T11 OUTPUT
syndrome_o[2:0] No No No OUTPUT
syndrome_o[4:3] Yes Yes T159 Yes T159 OUTPUT
syndrome_o[5] No No No OUTPUT
syndrome_o[6] Yes Yes *T159 Yes T159 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T159 Yes T159 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T159 Yes T159 OUTPUT
syndrome_o[2:1] No No No OUTPUT
syndrome_o[4:3] Yes Yes T159 Yes T159 OUTPUT
syndrome_o[7:5] No No No OUTPUT
err_o[0] Yes Yes *T159 Yes T159 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T2,T3,T11 Yes T2,T3,T11 INPUT
data_o[63:0] Yes Yes T2,T3,T11 Yes T2,T3,T11 OUTPUT
syndrome_o[0] Yes Yes *T154 Yes T154 OUTPUT
syndrome_o[3:1] No No No OUTPUT
syndrome_o[5:4] Yes Yes T154 Yes T154 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T154 Yes T154 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 282 96.58
Total Bits 0->1 146 141 96.58
Total Bits 1->0 146 141 96.58

Ports 4 2 50.00
Port Bits 292 282 96.58
Port Bits 0->1 146 141 96.58
Port Bits 1->0 146 141 96.58

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T61,*T155,*T160 Yes T61,T155,T160 OUTPUT
syndrome_o[3:1] No No No OUTPUT
syndrome_o[6:4] Yes Yes *T61,*T155,*T160 Yes T61,T155,T160 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T61,*T155,*T160 Yes T61,T155,T160 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 282 96.58
Total Bits 0->1 146 141 96.58
Total Bits 1->0 146 141 96.58

Ports 4 2 50.00
Port Bits 292 282 96.58
Port Bits 0->1 146 141 96.58
Port Bits 1->0 146 141 96.58

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 OUTPUT
syndrome_o[2:0] No No No OUTPUT
syndrome_o[6:3] Yes Yes *T155,*T154 Yes T155,T154 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T154,*T155 Yes T154,T155 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 282 96.58
Total Bits 0->1 146 141 96.58
Total Bits 1->0 146 141 96.58

Ports 4 2 50.00
Port Bits 292 282 96.58
Port Bits 0->1 146 141 96.58
Port Bits 1->0 146 141 96.58

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[1:0] No No No OUTPUT
syndrome_o[3:2] Yes Yes T158,T161 Yes T158,T161 OUTPUT
syndrome_o[4] No No No OUTPUT
syndrome_o[6:5] Yes Yes *T161,*T158 Yes T161,T158 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T158,*T161 Yes T158,T161 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 284 97.26
Total Bits 0->1 146 142 97.26
Total Bits 1->0 146 142 97.26

Ports 4 2 50.00
Port Bits 292 284 97.26
Port Bits 0->1 146 142 97.26
Port Bits 1->0 146 142 97.26

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T11 Yes T1,T2,T3 OUTPUT
syndrome_o[0] No No No OUTPUT
syndrome_o[3:1] Yes Yes T162 Yes T162 OUTPUT
syndrome_o[5:4] No No No OUTPUT
syndrome_o[7:6] Yes Yes T162 Yes T162 OUTPUT
err_o[0] Yes Yes *T162 Yes T162 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 286 97.95
Total Bits 0->1 146 143 97.95
Total Bits 1->0 146 143 97.95

Ports 4 2 50.00
Port Bits 292 286 97.95
Port Bits 0->1 146 143 97.95
Port Bits 1->0 146 143 97.95

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[4:0] Yes Yes T163 Yes T163 OUTPUT
syndrome_o[5] No No No OUTPUT
syndrome_o[6] Yes Yes *T163 Yes T163 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] No No No OUTPUT
err_o[1] Yes Yes T163 Yes T163 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 292 290 99.32
Total Bits 0->1 146 145 99.32
Total Bits 1->0 146 145 99.32

Ports 4 3 75.00
Port Bits 292 290 99.32
Port Bits 0->1 146 145 99.32
Port Bits 1->0 146 145 99.32

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T160 Yes T160 OUTPUT
syndrome_o[1] No No No OUTPUT
syndrome_o[7:2] Yes Yes T164,T160 Yes T164,T160 OUTPUT
err_o[1:0] Yes Yes T160,T164 Yes T160,T164 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%