Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23595487	16553	0	0
attest_sw_binding_0_rd_A	23595487	3399	0	0
attest_sw_binding_1_rd_A	23595487	3306	0	0
attest_sw_binding_2_rd_A	23595487	3303	0	0
attest_sw_binding_3_rd_A	23595487	3348	0	0
attest_sw_binding_4_rd_A	23595487	3370	0	0
attest_sw_binding_5_rd_A	23595487	3367	0	0
attest_sw_binding_6_rd_A	23595487	3451	0	0
attest_sw_binding_7_rd_A	23595487	3448	0	0
intr_enable_rd_A	23595487	3940	0	0
key_version_rd_A	23595487	3494	0	0
max_creator_key_ver_regwen_rd_A	23595487	3340	0	0
max_owner_int_key_ver_regwen_rd_A	23595487	3332	0	0
max_owner_key_ver_regwen_rd_A	23595487	3507	0	0
reseed_interval_regwen_rd_A	23595487	3275	0	0
salt_0_rd_A	23595487	3252	0	0
salt_1_rd_A	23595487	3309	0	0
salt_2_rd_A	23595487	3195	0	0
salt_3_rd_A	23595487	3355	0	0
salt_4_rd_A	23595487	3528	0	0
salt_5_rd_A	23595487	3443	0	0
salt_6_rd_A	23595487	3570	0	0
salt_7_rd_A	23595487	3473	0	0
sealing_sw_binding_0_rd_A	23595487	3404	0	0
sealing_sw_binding_1_rd_A	23595487	3419	0	0
sealing_sw_binding_2_rd_A	23595487	3348	0	0
sealing_sw_binding_3_rd_A	23595487	3325	0	0
sealing_sw_binding_4_rd_A	23595487	3488	0	0
sealing_sw_binding_5_rd_A	23595487	3441	0	0
sealing_sw_binding_6_rd_A	23595487	3360	0	0
sealing_sw_binding_7_rd_A	23595487	3351	0	0
sideload_clear_rd_A	23595487	3534	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	16553	0	0
T2	34834	108	0	0
T3	72661	0	0	0
T4	76622	0	0	0
T11	105574	0	0	0
T12	3973	0	0	0
T13	6242	0	0	0
T14	17504	0	0	0
T15	30015	0	0	0
T16	7147	0	0	0
T40	23780	0	0	0
T46	0	89	0	0
T50	0	1128	0	0
T54	0	311	0	0
T59	0	118	0	0
T60	0	17	0	0
T66	0	283	0	0
T67	0	29	0	0
T110	0	38	0	0
T111	0	558	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3399	0	0
T34	19257	0	0	0
T44	0	55	0	0
T67	26637	14	0	0
T102	0	105	0	0
T132	0	83	0	0
T154	4998	0	0	0
T166	0	20	0	0
T167	0	44	0	0
T168	0	20	0	0
T169	0	38	0	0
T170	0	17	0	0
T171	0	21	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3306	0	0
T34	19257	0	0	0
T44	0	52	0	0
T67	26637	23	0	0
T102	0	94	0	0
T132	0	78	0	0
T154	4998	0	0	0
T166	0	22	0	0
T167	0	25	0	0
T168	0	31	0	0
T169	0	35	0	0
T170	0	24	0	0
T171	0	20	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3303	0	0
T34	19257	0	0	0
T44	0	38	0	0
T67	26637	34	0	0
T102	0	109	0	0
T132	0	91	0	0
T154	4998	0	0	0
T166	0	22	0	0
T167	0	10	0	0
T168	0	20	0	0
T169	0	17	0	0
T170	0	37	0	0
T171	0	28	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3348	0	0
T34	19257	0	0	0
T44	0	59	0	0
T67	26637	28	0	0
T102	0	99	0	0
T132	0	71	0	0
T154	4998	0	0	0
T166	0	32	0	0
T167	0	41	0	0
T168	0	18	0	0
T169	0	32	0	0
T170	0	29	0	0
T171	0	23	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3370	0	0
T44	0	70	0	0
T67	0	25	0	0
T73	9073	0	0	0
T90	638	0	0	0
T111	31453	0	0	0
T132	0	86	0	0
T166	0	32	0	0
T167	0	42	0	0
T168	0	38	0	0
T169	0	32	0	0
T170	0	20	0	0
T171	0	39	0	0
T179	8805	1	0	0
T180	1599	0	0	0
T181	5820	0	0	0
T182	7125	0	0	0
T183	4366	0	0	0
T184	6328	0	0	0
T185	3379	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3367	0	0
T34	19257	0	0	0
T44	0	35	0	0
T67	26637	28	0	0
T102	0	125	0	0
T132	0	70	0	0
T154	4998	0	0	0
T166	0	37	0	0
T167	0	30	0	0
T168	0	10	0	0
T169	0	37	0	0
T170	0	20	0	0
T171	0	41	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3451	0	0
T34	19257	0	0	0
T44	0	61	0	0
T67	26637	26	0	0
T102	0	117	0	0
T132	0	66	0	0
T154	4998	0	0	0
T166	0	13	0	0
T167	0	40	0	0
T168	0	9	0	0
T169	0	31	0	0
T170	0	34	0	0
T171	0	7	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3448	0	0
T34	19257	0	0	0
T44	0	66	0	0
T67	26637	17	0	0
T102	0	89	0	0
T132	0	75	0	0
T154	4998	0	0	0
T166	0	37	0	0
T167	0	28	0	0
T168	0	22	0	0
T169	0	56	0	0
T170	0	16	0	0
T171	0	19	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3940	0	0
T6	0	57	0	0
T39	0	18	0	0
T42	2486	0	0	0
T44	0	66	0	0
T48	245492	36	0	0
T49	4515	0	0	0
T56	45503	0	0	0
T57	90780	0	0	0
T67	0	29	0	0
T116	33378	0	0	0
T166	0	41	0	0
T167	0	56	0	0
T168	0	52	0	0
T186	0	83	0	0
T187	0	7	0	0
T188	1963	0	0	0
T189	10404	0	0	0
T190	6341	0	0	0
T191	31426	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3494	0	0
T34	19257	0	0	0
T44	0	65	0	0
T67	26637	27	0	0
T102	0	105	0	0
T132	0	77	0	0
T154	4998	0	0	0
T166	0	16	0	0
T167	0	42	0	0
T168	0	28	0	0
T169	0	36	0	0
T170	0	31	0	0
T171	0	17	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3340	0	0
T34	19257	0	0	0
T44	0	67	0	0
T67	26637	15	0	0
T102	0	101	0	0
T132	0	66	0	0
T154	4998	0	0	0
T166	0	19	0	0
T167	0	24	0	0
T168	0	18	0	0
T169	0	24	0	0
T170	0	27	0	0
T171	0	42	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3332	0	0
T34	19257	0	0	0
T44	0	53	0	0
T67	26637	21	0	0
T102	0	88	0	0
T132	0	57	0	0
T154	4998	0	0	0
T166	0	24	0	0
T167	0	21	0	0
T168	0	19	0	0
T169	0	14	0	0
T170	0	23	0	0
T171	0	29	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3507	0	0
T34	19257	0	0	0
T44	0	73	0	0
T67	26637	20	0	0
T102	0	89	0	0
T132	0	97	0	0
T154	4998	0	0	0
T166	0	40	0	0
T167	0	33	0	0
T168	0	24	0	0
T169	0	33	0	0
T170	0	32	0	0
T171	0	29	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3275	0	0
T34	19257	0	0	0
T44	0	54	0	0
T67	26637	27	0	0
T102	0	94	0	0
T132	0	56	0	0
T154	4998	0	0	0
T166	0	28	0	0
T167	0	32	0	0
T168	0	33	0	0
T169	0	39	0	0
T170	0	21	0	0
T171	0	12	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3252	0	0
T34	19257	0	0	0
T44	0	46	0	0
T67	26637	28	0	0
T102	0	115	0	0
T132	0	97	0	0
T154	4998	0	0	0
T166	0	25	0	0
T167	0	20	0	0
T168	0	20	0	0
T169	0	23	0	0
T170	0	30	0	0
T171	0	10	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3309	0	0
T34	19257	0	0	0
T44	0	48	0	0
T67	26637	19	0	0
T102	0	78	0	0
T132	0	80	0	0
T154	4998	0	0	0
T166	0	30	0	0
T167	0	22	0	0
T168	0	21	0	0
T169	0	20	0	0
T170	0	27	0	0
T171	0	18	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3195	0	0
T34	19257	0	0	0
T44	0	46	0	0
T67	26637	20	0	0
T102	0	82	0	0
T132	0	86	0	0
T154	4998	0	0	0
T166	0	23	0	0
T167	0	24	0	0
T168	0	33	0	0
T169	0	40	0	0
T170	0	31	0	0
T171	0	30	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3355	0	0
T34	19257	0	0	0
T44	0	56	0	0
T67	26637	14	0	0
T102	0	85	0	0
T132	0	85	0	0
T154	4998	0	0	0
T166	0	43	0	0
T167	0	38	0	0
T168	0	14	0	0
T169	0	34	0	0
T170	0	31	0	0
T171	0	38	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3528	0	0
T34	19257	0	0	0
T44	0	63	0	0
T67	26637	10	0	0
T102	0	96	0	0
T132	0	89	0	0
T154	4998	0	0	0
T166	0	23	0	0
T167	0	43	0	0
T168	0	18	0	0
T169	0	26	0	0
T170	0	18	0	0
T171	0	26	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3443	0	0
T34	19257	0	0	0
T44	0	82	0	0
T67	26637	41	0	0
T102	0	102	0	0
T132	0	68	0	0
T154	4998	0	0	0
T166	0	29	0	0
T167	0	42	0	0
T168	0	26	0	0
T169	0	40	0	0
T170	0	14	0	0
T171	0	36	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3570	0	0
T34	19257	0	0	0
T44	0	51	0	0
T67	26637	31	0	0
T102	0	111	0	0
T132	0	83	0	0
T154	4998	0	0	0
T166	0	27	0	0
T167	0	36	0	0
T168	0	26	0	0
T169	0	31	0	0
T170	0	33	0	0
T171	0	39	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3473	0	0
T34	19257	0	0	0
T44	0	98	0	0
T67	26637	32	0	0
T102	0	124	0	0
T132	0	98	0	0
T154	4998	0	0	0
T166	0	12	0	0
T167	0	42	0	0
T168	0	42	0	0
T169	0	23	0	0
T170	0	17	0	0
T171	0	35	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3404	0	0
T34	19257	0	0	0
T44	0	54	0	0
T67	26637	9	0	0
T102	0	83	0	0
T132	0	72	0	0
T154	4998	0	0	0
T166	0	25	0	0
T167	0	42	0	0
T168	0	39	0	0
T169	0	38	0	0
T170	0	30	0	0
T171	0	14	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3419	0	0
T34	19257	0	0	0
T44	0	62	0	0
T67	26637	24	0	0
T102	0	102	0	0
T132	0	101	0	0
T154	4998	0	0	0
T166	0	20	0	0
T167	0	23	0	0
T168	0	25	0	0
T169	0	56	0	0
T170	0	20	0	0
T171	0	32	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3348	0	0
T34	19257	0	0	0
T44	0	59	0	0
T67	26637	28	0	0
T102	0	84	0	0
T132	0	59	0	0
T154	4998	0	0	0
T166	0	32	0	0
T167	0	27	0	0
T168	0	42	0	0
T169	0	20	0	0
T170	0	14	0	0
T171	0	24	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3325	0	0
T34	19257	0	0	0
T44	0	52	0	0
T67	26637	14	0	0
T102	0	87	0	0
T132	0	67	0	0
T154	4998	0	0	0
T166	0	17	0	0
T167	0	22	0	0
T168	0	27	0	0
T169	0	20	0	0
T170	0	35	0	0
T171	0	44	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3488	0	0
T34	19257	0	0	0
T44	0	75	0	0
T67	26637	15	0	0
T102	0	92	0	0
T132	0	49	0	0
T154	4998	0	0	0
T166	0	39	0	0
T167	0	17	0	0
T168	0	33	0	0
T169	0	25	0	0
T170	0	21	0	0
T171	0	45	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3441	0	0
T34	19257	0	0	0
T44	0	65	0	0
T67	26637	28	0	0
T102	0	125	0	0
T132	0	82	0	0
T154	4998	0	0	0
T166	0	23	0	0
T167	0	13	0	0
T168	0	34	0	0
T169	0	53	0	0
T170	0	21	0	0
T171	0	28	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3360	0	0
T34	19257	0	0	0
T44	0	65	0	0
T67	26637	15	0	0
T102	0	112	0	0
T132	0	93	0	0
T154	4998	0	0	0
T166	0	32	0	0
T167	0	29	0	0
T168	0	18	0	0
T169	0	15	0	0
T170	0	14	0	0
T171	0	23	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3351	0	0
T34	19257	0	0	0
T44	0	56	0	0
T67	26637	19	0	0
T102	0	107	0	0
T132	0	93	0	0
T154	4998	0	0	0
T166	0	11	0	0
T167	0	35	0	0
T168	0	22	0	0
T169	0	30	0	0
T170	0	12	0	0
T171	0	14	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23595487	3534	0	0
T34	19257	0	0	0
T44	0	50	0	0
T67	26637	15	0	0
T102	0	115	0	0
T132	0	81	0	0
T154	4998	0	0	0
T166	0	17	0	0
T167	0	44	0	0
T168	0	11	0	0
T169	0	41	0	0
T170	0	25	0	0
T171	0	17	0	0
T172	4553	0	0	0
T173	8815	0	0	0
T174	3063	0	0	0
T175	12148	0	0	0
T176	22285	0	0	0
T177	4171	0	0	0
T178	2040	0	0	0