Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2928701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

616526

1

T1

198

T2

4976

T3

3677

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3125692	1			T1	1252		T2	17610		T3	356624
values[0x0]	208096	1			T1	69		T2	188		T3	1403
values[0x1]	211439	1			T1	51		T2	196		T3	1448

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2011852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1533375

1

T1

542

T2

8780

T3

121774

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16993	1			T1	2		T2	97		T3	1371
valid_sources[0x01]	11222	1			T1	3		T2	29		T3	1388
valid_sources[0x02]	11648	1			T2	49		T3	1366		T11	35
valid_sources[0x03]	12321	1			T1	12		T2	89		T3	1386
valid_sources[0x04]	11600	1			T2	25		T3	1361		T4	1
valid_sources[0x05]	12792	1			T1	8		T2	76		T3	1381
valid_sources[0x06]	11915	1			T1	1		T2	55		T3	1316
valid_sources[0x07]	13590	1			T1	4		T2	93		T3	1485
valid_sources[0x08]	11907	1			T1	6		T2	94		T3	1359
valid_sources[0x09]	13884	1			T1	4		T2	123		T3	1376
valid_sources[0x0a]	12705	1			T1	4		T2	35		T3	1416
valid_sources[0x0b]	12714	1			T1	6		T2	98		T3	1435
valid_sources[0x0c]	11835	1			T1	5		T2	61		T3	1411
valid_sources[0x0d]	11584	1			T1	8		T2	65		T3	1450
valid_sources[0x0e]	16321	1			T1	1		T2	26		T3	1357
valid_sources[0x0f]	11524	1			T1	4		T2	6		T3	1407
valid_sources[0x10]	12493	1			T1	5		T2	52		T3	1360
valid_sources[0x11]	13230	1			T1	1		T2	50		T3	1408
valid_sources[0x12]	13579	1			T1	5		T2	1719		T3	1367
valid_sources[0x13]	10991	1			T2	44		T3	1415		T4	1
valid_sources[0x14]	16171	1			T1	2		T2	106		T3	1431
valid_sources[0x15]	14444	1			T1	6		T2	61		T3	1482
valid_sources[0x16]	19903	1			T1	2		T2	69		T3	1360
valid_sources[0x17]	11311	1			T1	7		T2	57		T3	1467
valid_sources[0x18]	12014	1			T1	1		T2	39		T3	1389
valid_sources[0x19]	16417	1			T1	7		T2	41		T3	1428
valid_sources[0x1a]	17018	1			T1	4		T2	23		T3	1355
valid_sources[0x1b]	11598	1			T1	12		T2	55		T3	1473
valid_sources[0x1c]	41773	1			T1	14		T2	61		T3	1410
valid_sources[0x1d]	13031	1			T1	5		T2	27		T3	1475
valid_sources[0x1e]	24796	1			T1	5		T2	39		T3	1437
valid_sources[0x1f]	12651	1			T1	1		T2	63		T3	1359
valid_sources[0x20]	12280	1			T1	5		T2	93		T3	1382
valid_sources[0x21]	13816	1			T1	6		T2	51		T3	1423
valid_sources[0x22]	12127	1			T1	7		T2	65		T3	1430
valid_sources[0x23]	13757	1			T1	5		T2	46		T3	1433
valid_sources[0x24]	13618	1			T1	10		T2	51		T3	1410
valid_sources[0x25]	11790	1			T1	2		T2	29		T3	1367
valid_sources[0x26]	15633	1			T1	3		T2	73		T3	1414
valid_sources[0x27]	11924	1			T1	6		T2	68		T3	1349
valid_sources[0x28]	13403	1			T1	11		T2	70		T3	1375
valid_sources[0x29]	11543	1			T1	12		T2	50		T3	1473
valid_sources[0x2a]	12847	1			T1	6		T2	42		T3	1438
valid_sources[0x2b]	17265	1			T1	6		T2	77		T3	1392
valid_sources[0x2c]	12206	1			T1	9		T2	85		T3	1380
valid_sources[0x2d]	13385	1			T1	3		T2	39		T3	1433
valid_sources[0x2e]	12459	1			T1	14		T2	78		T3	1351
valid_sources[0x2f]	17889	1			T1	9		T2	41		T3	1400
valid_sources[0x30]	22317	1			T1	3		T2	59		T3	1396
valid_sources[0x31]	12482	1			T1	12		T2	61		T3	1369
valid_sources[0x32]	15668	1			T1	13		T2	36		T3	1413
valid_sources[0x33]	11218	1			T1	8		T2	83		T3	1415
valid_sources[0x34]	12718	1			T1	7		T2	76		T3	1349
valid_sources[0x35]	19494	1			T1	14		T2	62		T3	1409
valid_sources[0x36]	12109	1			T1	6		T2	73		T3	1470
valid_sources[0x37]	12070	1			T2	74		T3	1314		T11	46
valid_sources[0x38]	11403	1			T1	11		T2	125		T3	1399
valid_sources[0x39]	11928	1			T1	1		T2	58		T3	1396
valid_sources[0x3a]	12443	1			T1	17		T2	85		T3	1378
valid_sources[0x3b]	12968	1			T1	4		T2	79		T3	1376
valid_sources[0x3c]	13688	1			T1	2		T2	30		T3	1374
valid_sources[0x3d]	11063	1			T2	12		T3	1417		T11	36
valid_sources[0x3e]	11632	1			T1	5		T2	42		T3	1410
valid_sources[0x3f]	11574	1			T1	1		T2	40		T3	1379
valid_sources[0x40]	15498	1			T1	5		T2	46		T3	1413
valid_sources[0x41]	13151	1			T1	11		T2	73		T3	1378
valid_sources[0x42]	16936	1			T2	43		T3	1356		T11	46
valid_sources[0x43]	12333	1			T1	1		T2	49		T3	1443
valid_sources[0x44]	15843	1			T1	4		T2	37		T3	1439
valid_sources[0x45]	14170	1			T1	4		T2	40		T3	1378
valid_sources[0x46]	11358	1			T1	2		T2	74		T3	1445
valid_sources[0x47]	12074	1			T1	5		T2	44		T3	1418
valid_sources[0x48]	11440	1			T1	5		T2	106		T3	1354
valid_sources[0x49]	12575	1			T1	7		T2	32		T3	1340
valid_sources[0x4a]	12394	1			T1	14		T2	75		T3	1427
valid_sources[0x4b]	12424	1			T1	15		T2	46		T3	1343
valid_sources[0x4c]	11710	1			T1	7		T2	26		T3	1435
valid_sources[0x4d]	11962	1			T1	9		T2	20		T3	1467
valid_sources[0x4e]	12661	1			T1	3		T2	78		T3	1412
valid_sources[0x4f]	11566	1			T1	9		T2	52		T3	1348
valid_sources[0x50]	22426	1			T1	7		T2	43		T3	1411
valid_sources[0x51]	12416	1			T1	2		T2	76		T3	1370
valid_sources[0x52]	15314	1			T1	5		T2	37		T3	1455
valid_sources[0x53]	11530	1			T1	6		T2	95		T3	1304
valid_sources[0x54]	10929	1			T1	1		T2	91		T3	1421
valid_sources[0x55]	12264	1			T1	2		T2	31		T3	1443
valid_sources[0x56]	20936	1			T1	3		T2	72		T3	1426
valid_sources[0x57]	15428	1			T1	3		T2	67		T3	1493
valid_sources[0x58]	18888	1			T2	52		T3	1400		T4	2
valid_sources[0x59]	15564	1			T1	8		T2	57		T3	1482
valid_sources[0x5a]	11730	1			T1	10		T2	97		T3	1459
valid_sources[0x5b]	13443	1			T1	4		T2	44		T3	1355
valid_sources[0x5c]	11116	1			T1	2		T2	53		T3	1444
valid_sources[0x5d]	20173	1			T1	1		T2	54		T3	1349
valid_sources[0x5e]	11639	1			T1	3		T2	77		T3	1461
valid_sources[0x5f]	11347	1			T1	1		T2	103		T3	1439
valid_sources[0x60]	11757	1			T1	1		T2	147		T3	1400
valid_sources[0x61]	11571	1			T1	11		T2	81		T3	1351
valid_sources[0x62]	31118	1			T1	2		T2	17		T3	1435
valid_sources[0x63]	10847	1			T1	14		T2	72		T3	1429
valid_sources[0x64]	15863	1			T1	7		T2	52		T3	1518
valid_sources[0x65]	12727	1			T1	19		T2	28		T3	1457
valid_sources[0x66]	19418	1			T1	10		T2	113		T3	1415
valid_sources[0x67]	17716	1			T1	7		T2	106		T3	1375
valid_sources[0x68]	14677	1			T1	4		T2	41		T3	1442
valid_sources[0x69]	15758	1			T1	3		T2	18		T3	1392
valid_sources[0x6a]	13617	1			T2	82		T3	1377		T11	44
valid_sources[0x6b]	32407	1			T1	4		T2	26		T3	1386
valid_sources[0x6c]	10815	1			T1	6		T2	58		T3	1373
valid_sources[0x6d]	13226	1			T1	7		T2	60		T3	1328
valid_sources[0x6e]	12353	1			T1	4		T2	103		T3	1349
valid_sources[0x6f]	14907	1			T1	4		T2	55		T3	1411
valid_sources[0x70]	16778	1			T1	10		T2	62		T3	1466
valid_sources[0x71]	18547	1			T1	3		T2	31		T3	1426
valid_sources[0x72]	12948	1			T1	4		T2	76		T3	1439
valid_sources[0x73]	11046	1			T1	3		T2	93		T3	1448
valid_sources[0x74]	13672	1			T1	6		T2	108		T3	1435
valid_sources[0x75]	12056	1			T1	3		T2	77		T3	1477
valid_sources[0x76]	11266	1			T1	7		T2	27		T3	1369
valid_sources[0x77]	10751	1			T1	2		T2	26		T3	1496
valid_sources[0x78]	11339	1			T1	7		T2	125		T3	1329
valid_sources[0x79]	12892	1			T1	9		T2	93		T3	1422
valid_sources[0x7a]	12939	1			T1	6		T2	66		T3	1367
valid_sources[0x7b]	11347	1			T1	9		T2	84		T3	1335
valid_sources[0x7c]	13054	1			T1	3		T2	72		T3	1436
valid_sources[0x7d]	11224	1			T1	1		T2	49		T3	1405
valid_sources[0x7e]	14418	1			T1	2		T2	77		T3	1415
valid_sources[0x7f]	11139	1			T1	5		T2	40		T3	1405
valid_sources[0x80]	16088	1			T1	6		T2	80		T3	1381

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331495

1

T1

164

T2

4723

T3

1891

values[0x0]

all_enables

biggest_size

150044

1

T1

27

T2

129

T3

932

values[0x1]

all_enables

biggest_size

134987

1

T1

7

T2

124

T3

854