Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21892410	15303	0	0
attest_sw_binding_0_rd_A	21892410	2317	0	0
attest_sw_binding_1_rd_A	21892410	2201	0	0
attest_sw_binding_2_rd_A	21892410	2300	0	0
attest_sw_binding_3_rd_A	21892410	2326	0	0
attest_sw_binding_4_rd_A	21892410	2355	0	0
attest_sw_binding_5_rd_A	21892410	2356	0	0
attest_sw_binding_6_rd_A	21892410	2313	0	0
attest_sw_binding_7_rd_A	21892410	2148	0	0
intr_enable_rd_A	21892410	3053	0	0
key_version_rd_A	21892410	2471	0	0
max_creator_key_ver_regwen_rd_A	21892410	2421	0	0
max_owner_int_key_ver_regwen_rd_A	21892410	2358	0	0
max_owner_key_ver_regwen_rd_A	21892410	2445	0	0
reseed_interval_regwen_rd_A	21892410	2245	0	0
salt_0_rd_A	21892410	2321	0	0
salt_1_rd_A	21892410	2355	0	0
salt_2_rd_A	21892410	2339	0	0
salt_3_rd_A	21892410	2480	0	0
salt_4_rd_A	21892410	2409	0	0
salt_5_rd_A	21892410	2528	0	0
salt_6_rd_A	21892410	2417	0	0
salt_7_rd_A	21892410	2337	0	0
sealing_sw_binding_0_rd_A	21892410	2348	0	0
sealing_sw_binding_1_rd_A	21892410	2326	0	0
sealing_sw_binding_2_rd_A	21892410	2354	0	0
sealing_sw_binding_3_rd_A	21892410	2177	0	0
sealing_sw_binding_4_rd_A	21892410	2286	0	0
sealing_sw_binding_5_rd_A	21892410	2280	0	0
sealing_sw_binding_6_rd_A	21892410	2436	0	0
sealing_sw_binding_7_rd_A	21892410	2445	0	0
sideload_clear_rd_A	21892410	2323	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	15303	0	0
T24	8321	0	0	0
T25	16231	0	0	0
T28	15938	0	0	0
T42	0	312	0	0
T44	13968	0	0	0
T47	0	20	0	0
T51	0	200	0	0
T55	0	510	0	0
T56	0	883	0	0
T59	0	511	0	0
T81	11217	424	0	0
T115	85205	0	0	0
T120	0	84	0	0
T121	0	143	0	0
T122	0	685	0	0
T123	4229	0	0	0
T124	9197	0	0	0
T125	4840	0	0	0
T126	2848	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2317	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	16	0	0
T51	21865	11	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	58	0	0
T120	36588	36	0	0
T133	0	5	0	0
T162	4897	0	0	0
T174	0	26	0	0
T175	0	29	0	0
T176	0	56	0	0
T177	0	69	0	0
T178	0	35	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2201	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	32	0	0
T51	21865	35	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	70	0	0
T120	36588	10	0	0
T152	0	83	0	0
T162	4897	0	0	0
T174	0	19	0	0
T175	0	25	0	0
T176	0	58	0	0
T177	0	50	0	0
T178	0	34	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2300	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	21	0	0
T51	21865	25	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	75	0	0
T120	36588	24	0	0
T133	0	7	0	0
T162	4897	0	0	0
T174	0	11	0	0
T175	0	19	0	0
T176	0	70	0	0
T177	0	41	0	0
T178	0	32	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2326	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	22	0	0
T51	21865	34	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	59	0	0
T120	36588	49	0	0
T133	0	30	0	0
T162	4897	0	0	0
T174	0	36	0	0
T175	0	8	0	0
T176	0	67	0	0
T177	0	42	0	0
T178	0	23	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2355	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	17	0	0
T51	21865	39	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	82	0	0
T120	36588	39	0	0
T133	0	27	0	0
T162	4897	0	0	0
T174	0	38	0	0
T175	0	15	0	0
T176	0	24	0	0
T177	0	60	0	0
T178	0	31	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2356	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	21	0	0
T51	21865	50	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	72	0	0
T120	36588	69	0	0
T133	0	10	0	0
T162	4897	0	0	0
T174	0	38	0	0
T175	0	30	0	0
T176	0	49	0	0
T177	0	60	0	0
T178	0	38	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2313	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	13	0	0
T51	21865	31	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	72	0	0
T120	36588	44	0	0
T133	0	13	0	0
T162	4897	0	0	0
T174	0	19	0	0
T175	0	18	0	0
T176	0	60	0	0
T177	0	50	0	0
T178	0	16	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2148	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	18	0	0
T51	21865	33	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	73	0	0
T120	36588	35	0	0
T152	0	81	0	0
T162	4897	0	0	0
T174	0	17	0	0
T175	0	31	0	0
T176	0	41	0	0
T177	0	67	0	0
T178	0	16	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	3053	0	0
T24	8321	0	0	0
T25	16231	0	0	0
T33	31898	20	0	0
T34	2687	0	0	0
T44	13968	0	0	0
T47	0	25	0	0
T51	0	92	0	0
T58	0	56	0	0
T81	11217	0	0	0
T115	85205	0	0	0
T120	0	21	0	0
T123	4229	0	0	0
T124	9197	0	0	0
T125	4840	0	0	0
T174	0	52	0	0
T182	0	32	0	0
T183	0	4	0	0
T184	0	32	0	0
T185	0	16	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2471	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	32	0	0
T51	21865	20	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	100	0	0
T120	36588	29	0	0
T133	0	16	0	0
T162	4897	0	0	0
T174	0	18	0	0
T175	0	41	0	0
T176	0	60	0	0
T177	0	65	0	0
T178	0	36	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2421	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	13	0	0
T51	21865	35	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	84	0	0
T120	36588	16	0	0
T133	0	11	0	0
T162	4897	0	0	0
T174	0	25	0	0
T175	0	18	0	0
T176	0	38	0	0
T177	0	51	0	0
T178	0	24	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2358	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	36	0	0
T51	21865	34	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	89	0	0
T120	36588	39	0	0
T133	0	2	0	0
T162	4897	0	0	0
T174	0	17	0	0
T175	0	26	0	0
T176	0	29	0	0
T177	0	47	0	0
T178	0	28	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2445	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	23	0	0
T51	21865	11	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	73	0	0
T120	36588	42	0	0
T133	0	30	0	0
T162	4897	0	0	0
T174	0	18	0	0
T175	0	36	0	0
T176	0	45	0	0
T177	0	77	0	0
T178	0	29	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2245	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	29	0	0
T51	21865	26	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	66	0	0
T120	36588	41	0	0
T133	0	27	0	0
T162	4897	0	0	0
T174	0	17	0	0
T175	0	17	0	0
T176	0	65	0	0
T177	0	60	0	0
T178	0	23	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2321	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	29	0	0
T51	21865	44	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	62	0	0
T120	36588	32	0	0
T133	0	54	0	0
T162	4897	0	0	0
T174	0	36	0	0
T175	0	15	0	0
T176	0	47	0	0
T177	0	46	0	0
T178	0	24	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2355	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	21	0	0
T51	21865	35	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	79	0	0
T120	36588	29	0	0
T162	4897	0	0	0
T174	0	18	0	0
T175	0	22	0	0
T176	0	27	0	0
T177	0	66	0	0
T178	0	34	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0
T186	0	5	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2339	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	33	0	0
T51	21865	35	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	57	0	0
T120	36588	27	0	0
T133	0	31	0	0
T162	4897	0	0	0
T174	0	19	0	0
T175	0	17	0	0
T176	0	43	0	0
T177	0	29	0	0
T178	0	36	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2480	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	20	0	0
T51	21865	37	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	85	0	0
T120	36588	38	0	0
T133	0	25	0	0
T162	4897	0	0	0
T174	0	22	0	0
T175	0	35	0	0
T176	0	70	0	0
T177	0	57	0	0
T178	0	23	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2409	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	27	0	0
T51	21865	17	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	70	0	0
T120	36588	42	0	0
T133	0	18	0	0
T162	4897	0	0	0
T174	0	22	0	0
T175	0	21	0	0
T176	0	33	0	0
T177	0	65	0	0
T178	0	34	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2528	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	24	0	0
T51	21865	25	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	95	0	0
T120	36588	63	0	0
T133	0	24	0	0
T162	4897	0	0	0
T174	0	28	0	0
T175	0	23	0	0
T176	0	44	0	0
T177	0	70	0	0
T178	0	21	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2417	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	27	0	0
T51	21865	35	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	55	0	0
T120	36588	48	0	0
T133	0	35	0	0
T162	4897	0	0	0
T174	0	31	0	0
T175	0	22	0	0
T176	0	66	0	0
T177	0	57	0	0
T178	0	22	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2337	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	43	0	0
T51	21865	37	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	96	0	0
T120	36588	37	0	0
T133	0	20	0	0
T162	4897	0	0	0
T174	0	20	0	0
T175	0	36	0	0
T176	0	61	0	0
T177	0	58	0	0
T178	0	34	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2348	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	23	0	0
T51	21865	18	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	83	0	0
T120	36588	44	0	0
T133	0	24	0	0
T162	4897	0	0	0
T174	0	18	0	0
T175	0	29	0	0
T176	0	58	0	0
T177	0	85	0	0
T178	0	25	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2326	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	24	0	0
T51	21865	32	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	73	0	0
T120	36588	19	0	0
T133	0	26	0	0
T162	4897	0	0	0
T174	0	29	0	0
T175	0	26	0	0
T176	0	39	0	0
T177	0	51	0	0
T178	0	22	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2354	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	6	0	0
T51	21865	31	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	73	0	0
T120	36588	25	0	0
T133	0	5	0	0
T162	4897	0	0	0
T174	0	36	0	0
T175	0	10	0	0
T176	0	59	0	0
T177	0	38	0	0
T178	0	31	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2177	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	25	0	0
T51	21865	19	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	66	0	0
T120	36588	39	0	0
T133	0	18	0	0
T162	4897	0	0	0
T174	0	28	0	0
T175	0	40	0	0
T176	0	49	0	0
T177	0	48	0	0
T178	0	20	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2286	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	22	0	0
T51	21865	46	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	60	0	0
T120	36588	29	0	0
T133	0	29	0	0
T162	4897	0	0	0
T174	0	35	0	0
T175	0	36	0	0
T176	0	41	0	0
T177	0	60	0	0
T178	0	20	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2280	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	34	0	0
T51	21865	47	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	73	0	0
T120	36588	37	0	0
T133	0	1	0	0
T162	4897	0	0	0
T174	0	31	0	0
T175	0	15	0	0
T176	0	45	0	0
T177	0	44	0	0
T178	0	29	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2436	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	26	0	0
T51	21865	37	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	71	0	0
T120	36588	65	0	0
T133	0	7	0	0
T162	4897	0	0	0
T174	0	25	0	0
T175	0	32	0	0
T176	0	46	0	0
T177	0	39	0	0
T178	0	31	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2445	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	24	0	0
T51	21865	29	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	87	0	0
T120	36588	34	0	0
T133	0	28	0	0
T162	4897	0	0	0
T174	0	24	0	0
T175	0	43	0	0
T176	0	43	0	0
T177	0	39	0	0
T178	0	24	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21892410	2323	0	0
T20	13474	0	0	0
T43	5018	0	0	0
T47	0	22	0	0
T51	21865	26	0	0
T63	4092	0	0	0
T66	4567	0	0	0
T114	0	61	0	0
T120	36588	39	0	0
T133	0	41	0	0
T162	4897	0	0	0
T174	0	19	0	0
T175	0	9	0	0
T176	0	62	0	0
T177	0	50	0	0
T178	0	28	0	0
T179	4635	0	0	0
T180	1485	0	0	0
T181	32441	0	0	0