Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2850345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

626037

1

T1

239

T2

420

T3

368

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3052272	1			T1	684		T2	1968		T3	499
values[0x0]	209560	1			T1	73		T2	155		T3	149
values[0x1]	214550	1			T1	64		T2	187		T3	176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1961010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1515372

1

T1

378

T2

989

T3

475

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18504	1			T2	9		T11	10		T12	1
valid_sources[0x01]	12586	1			T2	10		T11	9		T12	1
valid_sources[0x02]	9888	1			T2	14		T11	21		T12	3
valid_sources[0x03]	12854	1			T2	4		T11	9		T14	5
valid_sources[0x04]	8738	1			T1	1		T2	6		T11	12
valid_sources[0x05]	9568	1			T2	8		T11	9		T12	9
valid_sources[0x06]	9344	1			T1	11		T2	11		T11	7
valid_sources[0x07]	74562	1			T1	12		T2	10		T11	12
valid_sources[0x08]	17309	1			T1	6		T2	2		T11	11
valid_sources[0x09]	9819	1			T1	3		T2	12		T11	12
valid_sources[0x0a]	9293	1			T2	6		T11	10		T14	2
valid_sources[0x0b]	9395	1			T1	3		T2	7		T11	7
valid_sources[0x0c]	15180	1			T2	6		T11	6		T12	2
valid_sources[0x0d]	9400	1			T2	8		T11	10		T12	1
valid_sources[0x0e]	17554	1			T2	4		T11	11		T12	5
valid_sources[0x0f]	10001	1			T1	4		T2	6		T11	11
valid_sources[0x10]	8883	1			T1	4		T2	10		T11	5
valid_sources[0x11]	11514	1			T2	7		T11	12		T16	12
valid_sources[0x12]	20319	1			T1	24		T2	16		T11	6
valid_sources[0x13]	9125	1			T1	6		T2	6		T11	9
valid_sources[0x14]	9181	1			T1	3		T2	9		T11	11
valid_sources[0x15]	20071	1			T2	9		T11	12		T12	3
valid_sources[0x16]	9106	1			T2	7		T11	19		T12	2
valid_sources[0x17]	12753	1			T1	9		T2	9		T11	8
valid_sources[0x18]	9622	1			T2	7		T11	9		T14	4
valid_sources[0x19]	10435	1			T1	4		T2	3		T11	7
valid_sources[0x1a]	8930	1			T2	14		T11	14		T14	8
valid_sources[0x1b]	26926	1			T1	3		T2	11		T11	15
valid_sources[0x1c]	9124	1			T1	2		T2	16		T11	6
valid_sources[0x1d]	10771	1			T1	2		T2	13		T11	9
valid_sources[0x1e]	20372	1			T1	1		T2	7		T11	10
valid_sources[0x1f]	15036	1			T1	3		T2	7		T11	9
valid_sources[0x20]	9475	1			T1	9		T2	4		T11	11
valid_sources[0x21]	11607	1			T1	16		T2	7		T11	11
valid_sources[0x22]	29748	1			T1	4		T2	7		T11	9
valid_sources[0x23]	15359	1			T2	6		T11	10		T12	5
valid_sources[0x24]	9462	1			T1	2		T2	15		T11	13
valid_sources[0x25]	9315	1			T2	7		T11	8		T12	4
valid_sources[0x26]	13025	1			T2	12		T11	13		T12	4
valid_sources[0x27]	10006	1			T2	18		T11	11		T14	4
valid_sources[0x28]	10126	1			T2	7		T11	16		T14	2
valid_sources[0x29]	16746	1			T1	7		T2	8		T11	7
valid_sources[0x2a]	9085	1			T2	18		T11	19		T12	2
valid_sources[0x2b]	9520	1			T2	11		T11	10		T12	5
valid_sources[0x2c]	11804	1			T1	13		T2	10		T11	2
valid_sources[0x2d]	9010	1			T2	15		T11	11		T14	1
valid_sources[0x2e]	9886	1			T1	2		T2	8		T11	8
valid_sources[0x2f]	13147	1			T2	15		T11	7		T16	4
valid_sources[0x30]	10699	1			T2	15		T11	13		T14	12
valid_sources[0x31]	10496	1			T2	14		T11	8		T12	6
valid_sources[0x32]	10510	1			T2	13		T11	7		T12	2
valid_sources[0x33]	10165	1			T1	1		T2	9		T11	6
valid_sources[0x34]	20915	1			T2	7		T11	11		T14	12
valid_sources[0x35]	10265	1			T2	17		T11	13		T12	2
valid_sources[0x36]	28607	1			T1	3		T2	14		T11	12
valid_sources[0x37]	10374	1			T1	4		T2	3		T11	9
valid_sources[0x38]	9628	1			T1	2		T2	11		T11	11
valid_sources[0x39]	10034	1			T1	9		T2	4		T11	9
valid_sources[0x3a]	9821	1			T1	1		T2	11		T11	2
valid_sources[0x3b]	11292	1			T1	4		T2	13		T11	11
valid_sources[0x3c]	8707	1			T2	7		T11	11		T12	2
valid_sources[0x3d]	9500	1			T1	4		T2	8		T11	8
valid_sources[0x3e]	17930	1			T2	13		T11	6		T12	1
valid_sources[0x3f]	13995	1			T1	4		T2	6		T11	12
valid_sources[0x40]	9024	1			T2	11		T11	15		T12	2
valid_sources[0x41]	20186	1			T1	5		T2	10		T11	10
valid_sources[0x42]	13903	1			T2	7		T11	16		T12	5
valid_sources[0x43]	13250	1			T1	1		T2	9		T11	6
valid_sources[0x44]	9837	1			T1	2		T2	7		T11	12
valid_sources[0x45]	12888	1			T1	9		T2	7		T11	11
valid_sources[0x46]	9618	1			T1	3		T2	8		T11	9
valid_sources[0x47]	12488	1			T1	3		T2	5		T11	7
valid_sources[0x48]	9563	1			T2	9		T11	16		T14	1
valid_sources[0x49]	15664	1			T2	10		T11	13		T12	1
valid_sources[0x4a]	8884	1			T2	6		T11	11		T12	1
valid_sources[0x4b]	9112	1			T1	1		T2	13		T11	7
valid_sources[0x4c]	10840	1			T1	1		T2	7		T11	14
valid_sources[0x4d]	10838	1			T1	2		T2	7		T11	11
valid_sources[0x4e]	10046	1			T1	13		T2	7		T11	13
valid_sources[0x4f]	9642	1			T2	3		T11	6		T14	2
valid_sources[0x50]	17431	1			T1	6		T2	12		T11	13
valid_sources[0x51]	10330	1			T2	5		T11	12		T12	2
valid_sources[0x52]	12653	1			T2	22		T11	13		T14	3
valid_sources[0x53]	13123	1			T2	10		T11	6		T12	3
valid_sources[0x54]	9565	1			T2	19		T11	11		T12	3
valid_sources[0x55]	13038	1			T1	1		T2	10		T11	10
valid_sources[0x56]	10138	1			T1	9		T2	9		T11	11
valid_sources[0x57]	9290	1			T2	4		T11	9		T12	2
valid_sources[0x58]	10835	1			T2	4		T11	17		T12	6
valid_sources[0x59]	62090	1			T1	15		T2	3		T11	12
valid_sources[0x5a]	9305	1			T1	12		T2	13		T11	8
valid_sources[0x5b]	9162	1			T2	4		T11	10		T12	10
valid_sources[0x5c]	9448	1			T2	12		T11	17		T12	2
valid_sources[0x5d]	17467	1			T2	8		T11	12		T12	2
valid_sources[0x5e]	10542	1			T1	1		T2	13		T11	13
valid_sources[0x5f]	9252	1			T1	15		T2	10		T11	12
valid_sources[0x60]	11805	1			T1	7		T2	9		T11	10
valid_sources[0x61]	10358	1			T2	6		T11	5		T14	11
valid_sources[0x62]	9524	1			T2	10		T11	10		T14	10
valid_sources[0x63]	9397	1			T2	10		T11	12		T12	2
valid_sources[0x64]	9894	1			T1	1		T2	4		T11	6
valid_sources[0x65]	12432	1			T1	4		T2	15		T11	9
valid_sources[0x66]	9108	1			T1	3		T2	5		T11	13
valid_sources[0x67]	11013	1			T2	12		T11	8		T12	10
valid_sources[0x68]	14764	1			T2	3		T11	7		T12	9
valid_sources[0x69]	9273	1			T2	7		T11	3		T12	3
valid_sources[0x6a]	9002	1			T1	3		T2	8		T11	8
valid_sources[0x6b]	11210	1			T2	5		T11	14		T14	1
valid_sources[0x6c]	9413	1			T2	10		T11	9		T12	3
valid_sources[0x6d]	20949	1			T2	9		T11	8		T12	4
valid_sources[0x6e]	9393	1			T1	6		T2	6		T11	11
valid_sources[0x6f]	9391	1			T1	1		T2	5		T11	5
valid_sources[0x70]	9017	1			T1	17		T2	5		T11	9
valid_sources[0x71]	10422	1			T1	8		T2	9		T11	9
valid_sources[0x72]	11721	1			T1	10		T2	8		T11	12
valid_sources[0x73]	9438	1			T2	11		T11	6		T12	2
valid_sources[0x74]	149276	1			T2	13		T11	7		T12	2
valid_sources[0x75]	9281	1			T1	16		T2	7		T11	4
valid_sources[0x76]	9969	1			T2	10		T11	11		T12	1
valid_sources[0x77]	9252	1			T2	13		T11	13		T12	3
valid_sources[0x78]	27587	1			T1	4		T2	12		T11	16
valid_sources[0x79]	11969	1			T2	14		T11	10		T12	2
valid_sources[0x7a]	8828	1			T1	2		T2	13		T11	11
valid_sources[0x7b]	9246	1			T2	15		T11	8		T12	5
valid_sources[0x7c]	10279	1			T1	8		T2	9		T11	8
valid_sources[0x7d]	10698	1			T2	13		T11	10		T14	18
valid_sources[0x7e]	9000	1			T2	16		T11	12		T12	1
valid_sources[0x7f]	10111	1			T2	12		T11	11		T12	5
valid_sources[0x80]	10506	1			T2	7		T11	9		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

340267

1

T1

194

T2

204

T3

167

values[0x0]

all_enables

biggest_size

149953

1

T1

31

T2

104

T3

95

values[0x1]

all_enables

biggest_size

135817

1

T1

14

T2

112

T3

106