Module Definition
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Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 7911 7911 0 0
OutputsKnown_A 192793968 191246391 0 0
gen_no_flops.OutputDelay_A 192793968 191246391 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7911 7911 0 0
T1 9 9 0 0
T2 9 9 0 0
T3 9 9 0 0
T11 9 9 0 0
T12 9 9 0 0
T13 9 9 0 0
T14 9 9 0 0
T15 9 9 0 0
T16 9 9 0 0
T17 9 9 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 192793968 191246391 0 0
T1 117018 115488 0 0
T2 68634 68148 0 0
T3 28881 28089 0 0
T11 102789 102294 0 0
T12 23373 22707 0 0
T13 19701 19161 0 0
T14 43605 42723 0 0
T15 9099 8496 0 0
T16 194238 193554 0 0
T17 77418 76320 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 192793968 191246391 0 0
T1 117018 115488 0 0
T2 68634 68148 0 0
T3 28881 28089 0 0
T11 102789 102294 0 0
T12 23373 22707 0 0
T13 19701 19161 0 0
T14 43605 42723 0 0
T15 9099 8496 0 0
T16 194238 193554 0 0
T17 77418 76320 0 0

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 879 879 0 0
OutputsKnown_A 21421552 21249599 0 0
gen_no_flops.OutputDelay_A 21421552 21249599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21421552 21249599 0 0
T1 13002 12832 0 0
T2 7626 7572 0 0
T3 3209 3121 0 0
T11 11421 11366 0 0
T12 2597 2523 0 0
T13 2189 2129 0 0
T14 4845 4747 0 0
T15 1011 944 0 0
T16 21582 21506 0 0
T17 8602 8480 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%