Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21421552 |
21249599 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21421552 |
21249599 |
0 |
0 |
T1 |
13002 |
12832 |
0 |
0 |
T2 |
7626 |
7572 |
0 |
0 |
T3 |
3209 |
3121 |
0 |
0 |
T11 |
11421 |
11366 |
0 |
0 |
T12 |
2597 |
2523 |
0 |
0 |
T13 |
2189 |
2129 |
0 |
0 |
T14 |
4845 |
4747 |
0 |
0 |
T15 |
1011 |
944 |
0 |
0 |
T16 |
21582 |
21506 |
0 |
0 |
T17 |
8602 |
8480 |
0 |
0 |