Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23047611	18783	0	0
attest_sw_binding_0_rd_A	23047611	3361	0	0
attest_sw_binding_1_rd_A	23047611	2988	0	0
attest_sw_binding_2_rd_A	23047611	3295	0	0
attest_sw_binding_3_rd_A	23047611	3239	0	0
attest_sw_binding_4_rd_A	23047611	3212	0	0
attest_sw_binding_5_rd_A	23047611	3193	0	0
attest_sw_binding_6_rd_A	23047611	3244	0	0
attest_sw_binding_7_rd_A	23047611	3285	0	0
intr_enable_rd_A	23047611	3800	0	0
key_version_rd_A	23047611	3103	0	0
max_creator_key_ver_regwen_rd_A	23047611	3151	0	0
max_owner_int_key_ver_regwen_rd_A	23047611	3213	0	0
max_owner_key_ver_regwen_rd_A	23047611	3392	0	0
reseed_interval_regwen_rd_A	23047611	3154	0	0
salt_0_rd_A	23047611	3352	0	0
salt_1_rd_A	23047611	3207	0	0
salt_2_rd_A	23047611	3022	0	0
salt_3_rd_A	23047611	3186	0	0
salt_4_rd_A	23047611	3285	0	0
salt_5_rd_A	23047611	3062	0	0
salt_6_rd_A	23047611	3093	0	0
salt_7_rd_A	23047611	3207	0	0
sealing_sw_binding_0_rd_A	23047611	3235	0	0
sealing_sw_binding_1_rd_A	23047611	3243	0	0
sealing_sw_binding_2_rd_A	23047611	3272	0	0
sealing_sw_binding_3_rd_A	23047611	3295	0	0
sealing_sw_binding_4_rd_A	23047611	3400	0	0
sealing_sw_binding_5_rd_A	23047611	3198	0	0
sealing_sw_binding_6_rd_A	23047611	3270	0	0
sealing_sw_binding_7_rd_A	23047611	3227	0	0
sideload_clear_rd_A	23047611	3264	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	18783	0	0
T24	53279	806	0	0
T35	19018	0	0	0
T36	12991	0	0	0
T45	35787	198	0	0
T46	4390	0	0	0
T53	8313	0	0	0
T60	0	304	0	0
T69	0	305	0	0
T70	0	710	0	0
T92	6381	0	0	0
T93	2998	0	0	0
T130	0	127	0	0
T131	0	806	0	0
T132	0	40	0	0
T133	0	135	0	0
T135	4209	0	0	0
T136	19984	0	0	0
T179	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3361	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	14	0	0
T69	0	57	0	0
T97	9394	0	0	0
T129	0	38	0	0
T130	50438	56	0	0
T132	0	18	0	0
T143	4020	0	0	0
T180	0	69	0	0
T181	0	17	0	0
T182	0	30	0	0
T183	0	57	0	0
T184	0	18	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	2988	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	39	0	0
T69	0	70	0	0
T97	9394	0	0	0
T129	0	48	0	0
T130	50438	30	0	0
T132	0	23	0	0
T143	4020	0	0	0
T180	0	39	0	0
T181	0	20	0	0
T182	0	25	0	0
T183	0	78	0	0
T184	0	11	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3295	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	30	0	0
T69	0	46	0	0
T97	9394	0	0	0
T129	0	66	0	0
T130	50438	47	0	0
T132	0	38	0	0
T143	4020	0	0	0
T180	0	55	0	0
T181	0	36	0	0
T182	0	30	0	0
T183	0	46	0	0
T184	0	7	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3239	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	32	0	0
T69	0	33	0	0
T97	9394	0	0	0
T129	0	38	0	0
T130	50438	65	0	0
T132	0	19	0	0
T143	4020	0	0	0
T180	0	68	0	0
T181	0	24	0	0
T182	0	37	0	0
T183	0	60	0	0
T184	0	6	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3212	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	32	0	0
T69	0	19	0	0
T97	9394	0	0	0
T129	0	54	0	0
T130	50438	49	0	0
T132	0	26	0	0
T143	4020	0	0	0
T180	0	61	0	0
T181	0	26	0	0
T182	0	60	0	0
T183	0	39	0	0
T184	0	19	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3193	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	42	0	0
T69	0	74	0	0
T97	9394	0	0	0
T129	0	67	0	0
T130	50438	55	0	0
T132	0	20	0	0
T143	4020	0	0	0
T180	0	66	0	0
T181	0	42	0	0
T182	0	44	0	0
T183	0	20	0	0
T184	0	7	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3244	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	21	0	0
T69	0	44	0	0
T97	9394	0	0	0
T129	0	61	0	0
T130	50438	47	0	0
T132	0	39	0	0
T143	4020	0	0	0
T180	0	70	0	0
T181	0	38	0	0
T182	0	25	0	0
T183	0	42	0	0
T184	0	2	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3285	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	23	0	0
T69	0	64	0	0
T97	9394	0	0	0
T129	0	67	0	0
T130	50438	75	0	0
T132	0	35	0	0
T143	4020	0	0	0
T180	0	38	0	0
T181	0	44	0	0
T182	0	11	0	0
T183	0	30	0	0
T184	0	15	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3800	0	0
T50	71307	56	0	0
T51	0	9	0	0
T56	0	32	0	0
T68	21723	0	0	0
T69	0	56	0	0
T84	4338	0	0	0
T85	6019	0	0	0
T86	19759	0	0	0
T87	45969	0	0	0
T88	4809	0	0	0
T89	10057	0	0	0
T90	3445	0	0	0
T91	1949	0	0	0
T130	0	85	0	0
T132	0	23	0	0
T180	0	75	0	0
T181	0	22	0	0
T190	0	21	0	0
T191	0	38	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3103	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	16	0	0
T69	0	36	0	0
T97	9394	0	0	0
T129	0	57	0	0
T130	50438	54	0	0
T132	0	22	0	0
T143	4020	0	0	0
T180	0	46	0	0
T181	0	33	0	0
T182	0	24	0	0
T183	0	50	0	0
T184	0	6	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3151	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	30	0	0
T69	0	58	0	0
T97	9394	0	0	0
T129	0	46	0	0
T130	50438	50	0	0
T132	0	12	0	0
T143	4020	0	0	0
T180	0	43	0	0
T181	0	31	0	0
T182	0	23	0	0
T183	0	73	0	0
T184	0	4	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3213	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	20	0	0
T69	0	49	0	0
T97	9394	0	0	0
T129	0	38	0	0
T130	50438	58	0	0
T132	0	22	0	0
T143	4020	0	0	0
T180	0	55	0	0
T181	0	26	0	0
T182	0	22	0	0
T183	0	62	0	0
T184	0	4	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3392	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	23	0	0
T69	0	50	0	0
T97	9394	0	0	0
T129	0	77	0	0
T130	50438	43	0	0
T132	0	33	0	0
T143	4020	0	0	0
T180	0	46	0	0
T181	0	49	0	0
T182	0	34	0	0
T183	0	47	0	0
T184	0	6	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3154	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	27	0	0
T69	0	60	0	0
T97	9394	0	0	0
T129	0	51	0	0
T130	50438	67	0	0
T132	0	7	0	0
T143	4020	0	0	0
T180	0	58	0	0
T181	0	30	0	0
T182	0	31	0	0
T183	0	32	0	0
T184	0	16	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3352	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	32	0	0
T69	0	35	0	0
T97	9394	0	0	0
T129	0	66	0	0
T130	50438	61	0	0
T132	0	33	0	0
T143	4020	0	0	0
T180	0	46	0	0
T181	0	40	0	0
T182	0	28	0	0
T183	0	59	0	0
T184	0	13	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3207	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	17	0	0
T69	0	61	0	0
T97	9394	0	0	0
T129	0	54	0	0
T130	50438	65	0	0
T132	0	25	0	0
T143	4020	0	0	0
T180	0	36	0	0
T181	0	34	0	0
T182	0	20	0	0
T183	0	47	0	0
T184	0	12	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3022	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	27	0	0
T69	0	51	0	0
T97	9394	0	0	0
T129	0	66	0	0
T130	50438	53	0	0
T132	0	25	0	0
T143	4020	0	0	0
T180	0	33	0	0
T181	0	17	0	0
T182	0	16	0	0
T183	0	51	0	0
T184	0	14	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3186	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	8	0	0
T69	0	60	0	0
T97	9394	0	0	0
T129	0	41	0	0
T130	50438	42	0	0
T132	0	32	0	0
T143	4020	0	0	0
T180	0	31	0	0
T181	0	29	0	0
T182	0	64	0	0
T183	0	75	0	0
T184	0	6	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3285	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	17	0	0
T69	0	68	0	0
T97	9394	0	0	0
T129	0	46	0	0
T130	50438	69	0	0
T132	0	25	0	0
T143	4020	0	0	0
T180	0	46	0	0
T181	0	22	0	0
T182	0	25	0	0
T183	0	31	0	0
T184	0	16	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3062	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	26	0	0
T69	0	59	0	0
T97	9394	0	0	0
T129	0	60	0	0
T130	50438	52	0	0
T132	0	19	0	0
T143	4020	0	0	0
T180	0	41	0	0
T181	0	33	0	0
T182	0	49	0	0
T183	0	36	0	0
T184	0	8	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3093	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	27	0	0
T69	0	67	0	0
T97	9394	0	0	0
T129	0	61	0	0
T130	50438	35	0	0
T132	0	25	0	0
T143	4020	0	0	0
T180	0	49	0	0
T181	0	24	0	0
T182	0	22	0	0
T183	0	68	0	0
T184	0	19	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3207	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	28	0	0
T69	0	55	0	0
T97	9394	0	0	0
T129	0	43	0	0
T130	50438	52	0	0
T132	0	27	0	0
T143	4020	0	0	0
T180	0	48	0	0
T181	0	39	0	0
T182	0	25	0	0
T183	0	63	0	0
T184	0	9	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3235	0	0
T4	19409	0	0	0
T42	8567	5	0	0
T56	0	18	0	0
T67	6548	0	0	0
T69	0	44	0	0
T103	72097	0	0	0
T130	0	56	0	0
T132	0	19	0	0
T154	3852	0	0	0
T180	0	41	0	0
T181	0	29	0	0
T182	0	19	0	0
T183	0	48	0	0
T184	0	7	0	0
T192	6891	0	0	0
T193	9525	0	0	0
T194	47052	0	0	0
T195	861	0	0	0
T196	25969	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3243	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	23	0	0
T69	0	47	0	0
T97	9394	0	0	0
T129	0	43	0	0
T130	50438	58	0	0
T132	0	47	0	0
T143	4020	0	0	0
T180	0	60	0	0
T181	0	13	0	0
T182	0	34	0	0
T183	0	35	0	0
T184	0	3	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3272	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	15	0	0
T69	0	61	0	0
T97	9394	0	0	0
T129	0	65	0	0
T130	50438	51	0	0
T132	0	40	0	0
T143	4020	0	0	0
T180	0	58	0	0
T181	0	26	0	0
T182	0	23	0	0
T183	0	50	0	0
T184	0	14	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3295	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	17	0	0
T69	0	55	0	0
T97	9394	0	0	0
T129	0	66	0	0
T130	50438	89	0	0
T132	0	49	0	0
T143	4020	0	0	0
T180	0	39	0	0
T181	0	40	0	0
T182	0	19	0	0
T183	0	46	0	0
T184	0	7	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3400	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	58	0	0
T69	0	48	0	0
T97	9394	0	0	0
T129	0	69	0	0
T130	50438	65	0	0
T132	0	28	0	0
T143	4020	0	0	0
T180	0	68	0	0
T181	0	31	0	0
T182	0	20	0	0
T183	0	64	0	0
T184	0	9	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3198	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	33	0	0
T69	0	39	0	0
T97	9394	0	0	0
T129	0	54	0	0
T130	50438	59	0	0
T132	0	26	0	0
T143	4020	0	0	0
T180	0	41	0	0
T181	0	27	0	0
T182	0	47	0	0
T183	0	34	0	0
T184	0	5	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3270	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	28	0	0
T69	0	59	0	0
T97	9394	0	0	0
T129	0	30	0	0
T130	50438	37	0	0
T132	0	29	0	0
T143	4020	0	0	0
T180	0	46	0	0
T181	0	32	0	0
T182	0	37	0	0
T183	0	54	0	0
T184	0	9	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3227	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	21	0	0
T69	0	82	0	0
T97	9394	0	0	0
T129	0	54	0	0
T130	50438	55	0	0
T132	0	29	0	0
T143	4020	0	0	0
T180	0	44	0	0
T181	0	24	0	0
T182	0	28	0	0
T183	0	42	0	0
T184	0	6	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23047611	3264	0	0
T21	6042	0	0	0
T26	6625	0	0	0
T56	0	12	0	0
T69	0	76	0	0
T97	9394	0	0	0
T129	0	56	0	0
T130	50438	47	0	0
T132	0	45	0	0
T143	4020	0	0	0
T180	0	61	0	0
T181	0	18	0	0
T182	0	43	0	0
T183	0	39	0	0
T184	0	6	0	0
T185	12889	0	0	0
T186	4438	0	0	0
T187	11916	0	0	0
T188	4701	0	0	0
T189	11123	0	0	0