Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3283565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

639212

1

T1

1291

T2

140

T3

1974

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3496738	1			T1	2011		T2	660		T3	8581
values[0x0]	212243	1			T1	345		T2	33		T3	687
values[0x1]	213796	1			T1	396		T2	50		T3	704

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2251434	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1671343

1

T1

1664

T2

344

T3

4494

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10804	1			T15	190		T16	7		T17	12
valid_sources[0x01]	10986	1			T15	180		T16	6		T17	4
valid_sources[0x02]	11079	1			T15	166		T16	2		T18	11
valid_sources[0x03]	13066	1			T3	24		T15	178		T16	7
valid_sources[0x04]	12807	1			T15	208		T16	7		T17	3
valid_sources[0x05]	16273	1			T3	4		T15	204		T16	3
valid_sources[0x06]	100801	1			T3	5		T15	214		T16	6
valid_sources[0x07]	11668	1			T15	184		T16	3		T17	7
valid_sources[0x08]	11377	1			T14	1		T15	210		T16	4
valid_sources[0x09]	17084	1			T1	7		T15	184		T16	6
valid_sources[0x0a]	12011	1			T3	867		T15	193		T16	4
valid_sources[0x0b]	12854	1			T3	2		T15	210		T16	2
valid_sources[0x0c]	10926	1			T15	164		T16	8		T17	1
valid_sources[0x0d]	35990	1			T15	205		T16	5		T17	7
valid_sources[0x0e]	12855	1			T3	13		T12	1089		T14	3
valid_sources[0x0f]	11230	1			T1	21		T3	38		T15	194
valid_sources[0x10]	16928	1			T15	181		T16	6		T17	7
valid_sources[0x11]	13144	1			T14	35		T15	199		T16	7
valid_sources[0x12]	12050	1			T14	12		T15	182		T16	2
valid_sources[0x13]	11961	1			T15	192		T16	13		T17	6
valid_sources[0x14]	15588	1			T15	191		T16	9		T17	7
valid_sources[0x15]	15662	1			T1	14		T3	5		T14	35
valid_sources[0x16]	17611	1			T1	29		T14	19		T15	184
valid_sources[0x17]	10755	1			T14	1		T15	177		T16	7
valid_sources[0x18]	11840	1			T1	15		T15	192		T16	14
valid_sources[0x19]	12638	1			T15	188		T16	6		T17	3
valid_sources[0x1a]	17578	1			T15	177		T16	7		T17	9
valid_sources[0x1b]	12139	1			T15	200		T16	8		T17	2
valid_sources[0x1c]	40445	1			T15	181		T16	7		T17	6
valid_sources[0x1d]	16236	1			T15	164		T16	6		T17	2
valid_sources[0x1e]	11811	1			T15	217		T16	6		T17	6
valid_sources[0x1f]	11862	1			T14	17		T15	189		T16	5
valid_sources[0x20]	17523	1			T15	192		T16	6		T17	6
valid_sources[0x21]	12425	1			T15	168		T16	7		T17	2
valid_sources[0x22]	14538	1			T15	206		T16	8		T17	6
valid_sources[0x23]	20357	1			T15	177		T16	13		T17	5
valid_sources[0x24]	13081	1			T15	191		T16	8		T17	9
valid_sources[0x25]	19116	1			T3	49		T14	10		T15	162
valid_sources[0x26]	11787	1			T15	160		T16	1		T17	11
valid_sources[0x27]	11566	1			T1	92		T15	182		T16	5
valid_sources[0x28]	12133	1			T15	171		T16	3		T17	4
valid_sources[0x29]	11838	1			T15	178		T16	2		T17	5
valid_sources[0x2a]	50300	1			T1	15		T14	13		T15	216
valid_sources[0x2b]	17127	1			T15	175		T16	5		T17	7
valid_sources[0x2c]	10819	1			T15	191		T16	7		T17	6
valid_sources[0x2d]	16604	1			T1	9		T15	188		T16	2
valid_sources[0x2e]	16562	1			T3	2042		T15	209		T16	4
valid_sources[0x2f]	58552	1			T3	5		T14	11		T15	187
valid_sources[0x30]	11368	1			T15	195		T16	4		T17	3
valid_sources[0x31]	11817	1			T1	20		T15	190		T16	3
valid_sources[0x32]	13466	1			T15	194		T16	8		T17	3
valid_sources[0x33]	11442	1			T15	208		T16	3		T17	8
valid_sources[0x34]	11385	1			T15	206		T16	7		T17	2
valid_sources[0x35]	12352	1			T15	182		T16	7		T17	2
valid_sources[0x36]	11449	1			T3	10		T15	208		T16	7
valid_sources[0x37]	14385	1			T15	165		T16	3		T17	5
valid_sources[0x38]	17869	1			T15	199		T16	5		T17	6
valid_sources[0x39]	14041	1			T3	8		T14	27		T15	171
valid_sources[0x3a]	11662	1			T1	12		T14	18		T15	212
valid_sources[0x3b]	12525	1			T14	76		T15	207		T16	4
valid_sources[0x3c]	20773	1			T15	210		T16	5		T17	3
valid_sources[0x3d]	13333	1			T3	35		T15	187		T16	6
valid_sources[0x3e]	11560	1			T15	205		T16	8		T17	8
valid_sources[0x3f]	11034	1			T14	3		T15	205		T16	7
valid_sources[0x40]	14517	1			T3	1		T14	13		T15	202
valid_sources[0x41]	15867	1			T15	160		T16	8		T17	7
valid_sources[0x42]	12680	1			T3	63		T15	184		T16	5
valid_sources[0x43]	18834	1			T15	176		T16	2		T17	7
valid_sources[0x44]	12742	1			T14	53		T15	176		T16	7
valid_sources[0x45]	27558	1			T1	20		T15	206		T16	4
valid_sources[0x46]	31069	1			T15	206		T16	7		T17	11
valid_sources[0x47]	11407	1			T15	200		T16	3		T18	5
valid_sources[0x48]	12268	1			T1	5		T15	175		T16	9
valid_sources[0x49]	12316	1			T1	562		T15	194		T16	3
valid_sources[0x4a]	29452	1			T15	196		T16	6		T17	2
valid_sources[0x4b]	13936	1			T15	204		T16	7		T17	3
valid_sources[0x4c]	11205	1			T15	210		T16	4		T17	5
valid_sources[0x4d]	11041	1			T3	9		T15	162		T16	9
valid_sources[0x4e]	39485	1			T15	167		T16	13		T17	5
valid_sources[0x4f]	10996	1			T1	15		T3	5		T15	195
valid_sources[0x50]	11379	1			T1	522		T3	2		T15	192
valid_sources[0x51]	11231	1			T15	211		T16	1		T17	5
valid_sources[0x52]	14796	1			T15	183		T16	7		T17	11
valid_sources[0x53]	15365	1			T3	88		T15	200		T16	9
valid_sources[0x54]	11227	1			T15	173		T16	5		T17	10
valid_sources[0x55]	11779	1			T15	179		T16	8		T17	2
valid_sources[0x56]	10954	1			T15	170		T16	11		T17	3
valid_sources[0x57]	13526	1			T3	12		T15	189		T16	8
valid_sources[0x58]	20298	1			T15	228		T16	8		T17	6
valid_sources[0x59]	12221	1			T15	200		T16	8		T17	5
valid_sources[0x5a]	12516	1			T3	1295		T15	185		T16	8
valid_sources[0x5b]	11586	1			T15	187		T16	2		T17	4
valid_sources[0x5c]	11366	1			T3	62		T15	189		T16	6
valid_sources[0x5d]	13466	1			T3	44		T15	186		T16	5
valid_sources[0x5e]	12505	1			T3	18		T15	203		T16	8
valid_sources[0x5f]	12088	1			T3	7		T15	207		T16	7
valid_sources[0x60]	10905	1			T3	6		T15	171		T16	12
valid_sources[0x61]	31868	1			T3	4		T15	220		T16	7
valid_sources[0x62]	11125	1			T15	211		T16	4		T17	5
valid_sources[0x63]	13494	1			T15	224		T16	8		T17	2
valid_sources[0x64]	11596	1			T3	92		T15	197		T16	7
valid_sources[0x65]	11480	1			T15	195		T16	2		T17	2
valid_sources[0x66]	10894	1			T1	6		T15	173		T16	3
valid_sources[0x67]	11692	1			T1	105		T15	160		T16	4
valid_sources[0x68]	12795	1			T15	204		T16	8		T17	7
valid_sources[0x69]	10736	1			T15	203		T16	8		T18	18
valid_sources[0x6a]	11735	1			T3	29		T15	198		T16	5
valid_sources[0x6b]	11184	1			T3	12		T15	190		T16	2
valid_sources[0x6c]	12206	1			T15	178		T16	6		T17	6
valid_sources[0x6d]	19933	1			T15	195		T16	15		T17	7
valid_sources[0x6e]	14870	1			T15	192		T16	7		T17	9
valid_sources[0x6f]	11679	1			T3	2		T15	166		T16	9
valid_sources[0x70]	11659	1			T15	185		T16	6		T17	5
valid_sources[0x71]	11731	1			T14	5		T15	202		T16	8
valid_sources[0x72]	13756	1			T15	197		T16	7		T17	3
valid_sources[0x73]	90518	1			T14	49		T15	174		T16	3
valid_sources[0x74]	13657	1			T15	193		T16	1		T17	5
valid_sources[0x75]	12177	1			T15	199		T16	7		T17	6
valid_sources[0x76]	13744	1			T15	186		T16	3		T17	1
valid_sources[0x77]	32341	1			T15	174		T16	5		T17	5
valid_sources[0x78]	12821	1			T3	95		T15	185		T16	4
valid_sources[0x79]	29975	1			T3	6		T14	1		T15	163
valid_sources[0x7a]	11029	1			T15	191		T16	10		T17	1
valid_sources[0x7b]	12708	1			T3	44		T15	185		T16	1
valid_sources[0x7c]	22994	1			T1	13		T15	187		T16	12
valid_sources[0x7d]	11656	1			T15	205		T16	7		T17	5
valid_sources[0x7e]	11714	1			T3	21		T15	191		T16	10
valid_sources[0x7f]	12129	1			T15	169		T16	8		T18	5
valid_sources[0x80]	11772	1			T1	3		T15	211		T16	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

349325

1

T1

827

T2

114

T3

945

values[0x0]

all_enables

biggest_size

153110

1

T1

244

T2

14

T3

571

values[0x1]

all_enables

biggest_size

136777

1

T1

220

T2

12

T3

458