Line Coverage for Module :
prim_edn_req
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
ALWAYS | 143 | 3 | 3 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 163 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
139 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
146 |
1 |
1 |
149 |
1 |
1 |
163 |
|
unreachable |
164 |
|
unreachable |
165 |
|
unreachable |
166 |
|
unreachable |
167 |
|
unreachable |
168 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_edn_req
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (req_i & ((~ack_o)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (req_i && ack_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (fips_q & word_fips)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T15 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_edn_req
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
139 |
3 |
3 |
100.00 |
IF |
143 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 139 ((req_i && ack_o)) ?
-2-: 139 (word_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 143 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_edn_req
Assertion Details
DataOutputDiffFromPrev_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
13054204 |
0 |
0 |
T1 |
32865 |
14104 |
0 |
0 |
T2 |
9650 |
7848 |
0 |
0 |
T3 |
30802 |
11852 |
0 |
0 |
T4 |
0 |
356239 |
0 |
0 |
T12 |
10986 |
0 |
0 |
0 |
T13 |
15936 |
0 |
0 |
0 |
T14 |
3419 |
1913 |
0 |
0 |
T15 |
153486 |
130828 |
0 |
0 |
T16 |
17653 |
15805 |
0 |
0 |
T17 |
3938 |
2513 |
0 |
0 |
T18 |
10352 |
7255 |
0 |
0 |
T81 |
0 |
9895 |
0 |
0 |
DataOutputValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
53578 |
0 |
0 |
T1 |
32865 |
26 |
0 |
0 |
T2 |
9650 |
8 |
0 |
0 |
T3 |
30802 |
69 |
0 |
0 |
T12 |
10986 |
1 |
0 |
0 |
T13 |
15936 |
1 |
0 |
0 |
T14 |
3419 |
4 |
0 |
0 |
T15 |
153486 |
503 |
0 |
0 |
T16 |
17653 |
15 |
0 |
0 |
T17 |
3938 |
7 |
0 |
0 |
T18 |
10352 |
5 |
0 |
0 |