Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
23252296 |
23080916 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |