SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::PutFullData_mask_not_match_size | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::addr_not_align_mask | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::addr_not_align_size | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::invalid_a_opcode | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::mask_not_in_enabled_lanes | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::size_over_max | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 9663 | 1 | T5 | 282 | T46 | 314 | T104 | 397 | ||||
rising | 9660 | 1 | T5 | 282 | T46 | 315 | T104 | 397 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 39307 | 1 | T5 | 1126 | T46 | 1512 | T104 | 1560 | ||||
auto[1] | 13112 | 1 | T5 | 380 | T46 | 390 | T104 | 537 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 11759 | 1 | T5 | 358 | T46 | 437 | T104 | 457 | ||||
rising | 11758 | 1 | T5 | 358 | T46 | 437 | T104 | 457 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 34195 | 1 | T5 | 978 | T46 | 1240 | T104 | 1369 | ||||
auto[1] | 18224 | 1 | T5 | 528 | T46 | 662 | T104 | 728 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 11759 | 1 | T5 | 358 | T46 | 437 | T104 | 457 | ||||
rising | 11758 | 1 | T5 | 358 | T46 | 437 | T104 | 457 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 34195 | 1 | T5 | 978 | T46 | 1240 | T104 | 1369 | ||||
auto[1] | 18224 | 1 | T5 | 528 | T46 | 662 | T104 | 728 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 11458 | 1 | T5 | 347 | T46 | 461 | T104 | 463 | ||||
rising | 11463 | 1 | T5 | 348 | T46 | 461 | T104 | 462 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 34704 | 1 | T5 | 1000 | T46 | 1165 | T104 | 1385 | ||||
auto[1] | 17715 | 1 | T5 | 506 | T46 | 737 | T104 | 712 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 11155 | 1 | T5 | 316 | T46 | 396 | T104 | 466 | ||||
rising | 11157 | 1 | T5 | 315 | T46 | 395 | T104 | 466 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 36441 | 1 | T5 | 1067 | T46 | 1368 | T104 | 1431 | ||||
auto[1] | 15978 | 1 | T5 | 439 | T46 | 534 | T104 | 666 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 9879 | 1 | T5 | 313 | T46 | 331 | T104 | 395 | ||||
rising | 9873 | 1 | T5 | 313 | T46 | 331 | T104 | 395 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 39026 | 1 | T5 | 1083 | T46 | 1472 | T104 | 1557 | ||||
auto[1] | 13393 | 1 | T5 | 423 | T46 | 430 | T104 | 540 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |