Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2943453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

655078

1

T1

621

T2

414

T3

377

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3157788	1			T1	831		T2	383		T3	2186
values[0x0]	219500	1			T1	256		T2	161		T3	168
values[0x1]	221243	1			T1	255		T2	179		T3	162

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2025282	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1573249

1

T1

816

T2

482

T3

1025

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11308	1			T1	6		T2	3		T3	3
valid_sources[0x01]	12040	1			T1	3		T2	3		T15	7
valid_sources[0x02]	13886	1			T1	19		T2	2		T15	5
valid_sources[0x03]	10616	1			T1	3		T2	2		T16	43
valid_sources[0x04]	11300	1			T2	5		T3	11		T14	1
valid_sources[0x05]	20030	1			T1	9		T2	6		T3	4
valid_sources[0x06]	12852	1			T1	2		T2	4		T3	2
valid_sources[0x07]	13314	1			T1	8		T2	2		T16	50
valid_sources[0x08]	10536	1			T1	4		T2	2		T15	2
valid_sources[0x09]	13195	1			T1	9		T2	5		T3	44
valid_sources[0x0a]	11337	1			T1	4		T2	1		T16	43
valid_sources[0x0b]	15199	1			T1	4		T2	3		T15	1
valid_sources[0x0c]	11641	1			T1	7		T2	9		T15	3
valid_sources[0x0d]	16936	1			T1	8		T2	3		T3	19
valid_sources[0x0e]	10208	1			T1	5		T2	3		T3	24
valid_sources[0x0f]	11592	1			T1	8		T2	4		T3	21
valid_sources[0x10]	26693	1			T1	5		T15	8		T16	49
valid_sources[0x11]	19383	1			T1	6		T2	3		T3	44
valid_sources[0x12]	15993	1			T1	3		T2	4		T3	5
valid_sources[0x13]	10738	1			T1	9		T2	2		T3	15
valid_sources[0x14]	18529	1			T1	6		T2	3		T16	47
valid_sources[0x15]	11061	1			T1	7		T15	11		T16	36
valid_sources[0x16]	11573	1			T1	9		T2	2		T15	4
valid_sources[0x17]	10643	1			T1	1		T15	7		T16	24
valid_sources[0x18]	11091	1			T1	6		T2	3		T15	4
valid_sources[0x19]	10482	1			T1	10		T2	4		T3	20
valid_sources[0x1a]	12210	1			T1	6		T2	4		T3	59
valid_sources[0x1b]	11610	1			T1	5		T2	2		T3	3
valid_sources[0x1c]	10986	1			T2	2		T3	12		T16	35
valid_sources[0x1d]	23563	1			T1	8		T2	2		T16	34
valid_sources[0x1e]	16692	1			T1	1		T2	3		T15	9
valid_sources[0x1f]	11310	1			T1	6		T2	3		T15	27
valid_sources[0x20]	10244	1			T1	2		T2	2		T14	1
valid_sources[0x21]	10451	1			T1	5		T2	2		T15	11
valid_sources[0x22]	10475	1			T1	3		T2	1		T3	33
valid_sources[0x23]	11227	1			T1	3		T2	2		T3	32
valid_sources[0x24]	18292	1			T1	10		T15	3		T16	28
valid_sources[0x25]	10549	1			T1	5		T2	3		T3	26
valid_sources[0x26]	12779	1			T1	7		T2	1		T16	43
valid_sources[0x27]	13145	1			T1	3		T2	2		T14	1
valid_sources[0x28]	17022	1			T1	5		T2	4		T3	1
valid_sources[0x29]	10060	1			T1	4		T2	6		T3	11
valid_sources[0x2a]	14608	1			T1	4		T2	2		T3	4
valid_sources[0x2b]	11898	1			T1	6		T2	2		T15	27
valid_sources[0x2c]	10411	1			T1	13		T2	2		T3	21
valid_sources[0x2d]	21965	1			T1	4		T2	1		T15	3
valid_sources[0x2e]	17525	1			T1	3		T2	1		T3	6
valid_sources[0x2f]	19850	1			T1	4		T2	6		T3	28
valid_sources[0x30]	13492	1			T1	3		T2	1		T14	1
valid_sources[0x31]	20727	1			T1	8		T2	2		T15	10
valid_sources[0x32]	37831	1			T1	4		T2	7		T3	10
valid_sources[0x33]	10293	1			T1	7		T2	1		T15	1
valid_sources[0x34]	10502	1			T1	9		T2	4		T15	6
valid_sources[0x35]	11665	1			T1	5		T2	6		T3	43
valid_sources[0x36]	12969	1			T1	1		T2	8		T15	1
valid_sources[0x37]	13230	1			T1	9		T3	20		T16	21
valid_sources[0x38]	11133	1			T1	8		T2	2		T3	14
valid_sources[0x39]	13716	1			T1	9		T2	4		T14	1
valid_sources[0x3a]	10184	1			T1	2		T2	2		T3	15
valid_sources[0x3b]	10735	1			T1	4		T2	3		T16	36
valid_sources[0x3c]	10947	1			T1	2		T2	4		T15	3
valid_sources[0x3d]	10665	1			T1	6		T2	2		T3	14
valid_sources[0x3e]	11483	1			T1	3		T2	2		T14	1
valid_sources[0x3f]	11346	1			T1	4		T2	3		T3	12
valid_sources[0x40]	12069	1			T1	6		T2	3		T3	3
valid_sources[0x41]	14347	1			T1	4		T2	1		T14	1
valid_sources[0x42]	14532	1			T1	7		T2	1		T15	2
valid_sources[0x43]	13813	1			T1	9		T2	3		T3	3
valid_sources[0x44]	19480	1			T1	7		T2	1		T3	2
valid_sources[0x45]	15138	1			T1	4		T2	2		T3	18
valid_sources[0x46]	13466	1			T1	5		T15	3		T16	45
valid_sources[0x47]	12076	1			T1	2		T2	3		T15	6
valid_sources[0x48]	12902	1			T1	9		T2	5		T3	12
valid_sources[0x49]	10766	1			T1	3		T2	2		T16	40
valid_sources[0x4a]	14698	1			T1	2		T2	4		T3	9
valid_sources[0x4b]	11873	1			T2	4		T16	40		T18	2
valid_sources[0x4c]	13333	1			T1	9		T2	4		T3	24
valid_sources[0x4d]	11019	1			T1	15		T2	4		T3	74
valid_sources[0x4e]	13648	1			T1	3		T2	2		T3	5
valid_sources[0x4f]	10437	1			T1	1		T2	4		T15	2
valid_sources[0x50]	11840	1			T1	7		T3	6		T15	4
valid_sources[0x51]	10643	1			T1	4		T2	5		T15	4
valid_sources[0x52]	10466	1			T1	1		T2	1		T3	29
valid_sources[0x53]	16465	1			T1	3		T2	3		T3	3
valid_sources[0x54]	18767	1			T1	5		T2	4		T16	41
valid_sources[0x55]	14348	1			T1	9		T2	4		T3	23
valid_sources[0x56]	11620	1			T1	3		T15	4		T16	36
valid_sources[0x57]	10884	1			T1	5		T2	4		T16	64
valid_sources[0x58]	11454	1			T1	6		T16	34		T19	389
valid_sources[0x59]	12818	1			T1	1		T2	1		T15	2
valid_sources[0x5a]	10568	1			T1	7		T2	3		T3	94
valid_sources[0x5b]	10335	1			T1	4		T2	4		T3	13
valid_sources[0x5c]	14199	1			T1	3		T2	2		T15	6
valid_sources[0x5d]	16330	1			T1	13		T2	2		T3	31
valid_sources[0x5e]	20592	1			T1	3		T2	5		T3	8
valid_sources[0x5f]	11297	1			T1	4		T2	5		T3	39
valid_sources[0x60]	21019	1			T1	3		T2	2		T16	33
valid_sources[0x61]	10639	1			T1	6		T2	6		T3	10
valid_sources[0x62]	11323	1			T1	6		T2	3		T15	5
valid_sources[0x63]	14424	1			T1	4		T2	3		T3	20
valid_sources[0x64]	10646	1			T1	5		T2	1		T15	2
valid_sources[0x65]	13639	1			T1	4		T2	3		T3	7
valid_sources[0x66]	11430	1			T1	2		T2	4		T15	3
valid_sources[0x67]	10267	1			T1	5		T2	3		T15	2
valid_sources[0x68]	10998	1			T1	10		T2	1		T3	13
valid_sources[0x69]	10181	1			T1	5		T2	2		T15	2
valid_sources[0x6a]	35347	1			T1	4		T2	6		T3	35
valid_sources[0x6b]	13277	1			T1	3		T2	2		T3	30
valid_sources[0x6c]	12051	1			T1	4		T2	3		T15	4
valid_sources[0x6d]	19044	1			T1	6		T2	9		T3	3
valid_sources[0x6e]	11648	1			T1	12		T2	3		T3	32
valid_sources[0x6f]	11931	1			T1	2		T2	3		T3	32
valid_sources[0x70]	12999	1			T1	5		T2	1		T3	4
valid_sources[0x71]	10297	1			T1	6		T2	1		T3	26
valid_sources[0x72]	10749	1			T1	4		T2	1		T3	1
valid_sources[0x73]	10004	1			T1	4		T2	3		T3	6
valid_sources[0x74]	16782	1			T1	7		T2	3		T15	5
valid_sources[0x75]	10945	1			T1	3		T2	1		T15	1
valid_sources[0x76]	10673	1			T1	8		T2	4		T3	20
valid_sources[0x77]	12776	1			T1	9		T2	3		T15	6
valid_sources[0x78]	42256	1			T1	9		T2	1		T16	39
valid_sources[0x79]	13205	1			T2	3		T15	5		T16	34
valid_sources[0x7a]	12581	1			T1	4		T2	5		T16	23
valid_sources[0x7b]	10856	1			T1	3		T2	6		T3	12
valid_sources[0x7c]	10026	1			T1	2		T2	3		T15	6
valid_sources[0x7d]	12110	1			T1	6		T2	4		T15	11
valid_sources[0x7e]	11109	1			T1	12		T2	6		T15	7
valid_sources[0x7f]	18840	1			T1	5		T2	1		T3	38
valid_sources[0x80]	12851	1			T1	7		T2	5		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

355103

1

T1

309

T2

171

T3

160

values[0x0]

all_enables

biggest_size

158103

1

T1

162

T2

113

T3

113

values[0x1]

all_enables

biggest_size

141872

1

T1

150

T2

130

T3

104