Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
20813951 |
20642276 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20813951 |
20642276 |
0 |
0 |
T1 |
4546 |
4418 |
0 |
0 |
T2 |
7969 |
7902 |
0 |
0 |
T3 |
21608 |
21555 |
0 |
0 |
T4 |
13946 |
13858 |
0 |
0 |
T14 |
1498 |
1418 |
0 |
0 |
T15 |
14359 |
14283 |
0 |
0 |
T16 |
127442 |
127390 |
0 |
0 |
T17 |
5079 |
5004 |
0 |
0 |
T18 |
2387 |
2306 |
0 |
0 |
T19 |
184051 |
183990 |
0 |
0 |