Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3184007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

643982

1

T1

268

T2

231

T3

339

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3396926	1			T1	941		T2	2751		T3	2598
values[0x0]	213831	1			T1	53		T2	75		T3	150
values[0x1]	217232	1			T1	71		T2	61		T3	151

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2183403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1644586

1

T1

505

T2

1065

T3

1149

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15701	1			T1	9		T2	8		T3	5
valid_sources[0x01]	13295	1			T2	12		T3	15		T7	2
valid_sources[0x02]	11839	1			T1	4		T2	10		T3	11
valid_sources[0x03]	12740	1			T1	1		T2	14		T3	13
valid_sources[0x04]	12400	1			T1	2		T2	13		T3	8
valid_sources[0x05]	14713	1			T1	1		T2	12		T3	12
valid_sources[0x06]	14011	1			T1	6		T2	13		T3	12
valid_sources[0x07]	11771	1			T2	7		T3	13		T7	5
valid_sources[0x08]	14362	1			T1	4		T2	10		T3	6
valid_sources[0x09]	18151	1			T1	4		T2	13		T3	12
valid_sources[0x0a]	12609	1			T1	1		T2	14		T3	8
valid_sources[0x0b]	12025	1			T1	1		T2	9		T3	7
valid_sources[0x0c]	12606	1			T1	11		T2	15		T3	14
valid_sources[0x0d]	14407	1			T1	6		T2	10		T3	11
valid_sources[0x0e]	19042	1			T1	8		T2	16		T3	12
valid_sources[0x0f]	11295	1			T1	7		T2	7		T3	14
valid_sources[0x10]	15012	1			T1	2		T2	11		T3	11
valid_sources[0x11]	15630	1			T1	11		T2	8		T3	18
valid_sources[0x12]	13034	1			T1	8		T2	16		T3	10
valid_sources[0x13]	26266	1			T1	3		T2	11		T3	11
valid_sources[0x14]	17257	1			T1	8		T2	18		T3	12
valid_sources[0x15]	11676	1			T1	5		T2	8		T3	15
valid_sources[0x16]	11997	1			T2	6		T3	17		T7	2
valid_sources[0x17]	11912	1			T2	16		T3	16		T7	2
valid_sources[0x18]	12583	1			T2	11		T3	11		T11	12
valid_sources[0x19]	12459	1			T1	4		T2	19		T3	8
valid_sources[0x1a]	13391	1			T1	9		T2	16		T3	9
valid_sources[0x1b]	15054	1			T1	9		T2	5		T3	16
valid_sources[0x1c]	12013	1			T1	6		T2	12		T3	7
valid_sources[0x1d]	15582	1			T1	8		T2	13		T3	15
valid_sources[0x1e]	12673	1			T1	2		T2	9		T3	9
valid_sources[0x1f]	11378	1			T1	18		T2	14		T3	14
valid_sources[0x20]	37168	1			T1	9		T2	15		T3	13
valid_sources[0x21]	19850	1			T1	9		T2	13		T3	15
valid_sources[0x22]	22894	1			T1	14		T2	6		T3	9
valid_sources[0x23]	11508	1			T1	1		T2	10		T3	9
valid_sources[0x24]	11879	1			T2	11		T3	10		T11	7
valid_sources[0x25]	12681	1			T2	9		T3	13		T11	22
valid_sources[0x26]	11770	1			T2	16		T3	8		T7	2
valid_sources[0x27]	12528	1			T1	2		T2	10		T3	11
valid_sources[0x28]	19089	1			T2	11		T3	10		T7	4
valid_sources[0x29]	11457	1			T1	5		T2	6		T3	14
valid_sources[0x2a]	15134	1			T1	1		T2	13		T3	17
valid_sources[0x2b]	11917	1			T2	10		T3	5		T11	12
valid_sources[0x2c]	25415	1			T2	6		T3	6		T11	17
valid_sources[0x2d]	13342	1			T1	4		T2	20		T3	5
valid_sources[0x2e]	19318	1			T1	9		T2	13		T3	8
valid_sources[0x2f]	12401	1			T1	2		T2	13		T3	12
valid_sources[0x30]	12704	1			T1	3		T2	9		T3	8
valid_sources[0x31]	12443	1			T1	1		T2	10		T3	5
valid_sources[0x32]	14431	1			T1	6		T2	8		T3	8
valid_sources[0x33]	12818	1			T1	17		T2	12		T3	10
valid_sources[0x34]	12977	1			T1	4		T2	14		T3	8
valid_sources[0x35]	35618	1			T1	13		T2	13		T3	13
valid_sources[0x36]	12393	1			T2	7		T3	10		T11	12
valid_sources[0x37]	14469	1			T2	9		T3	8		T7	5
valid_sources[0x38]	13310	1			T2	14		T3	12		T7	7
valid_sources[0x39]	12357	1			T1	11		T2	8		T3	14
valid_sources[0x3a]	11425	1			T1	1		T2	10		T3	13
valid_sources[0x3b]	12318	1			T1	7		T2	11		T3	10
valid_sources[0x3c]	21816	1			T1	7		T2	12		T3	7
valid_sources[0x3d]	18696	1			T2	8		T3	13		T11	4
valid_sources[0x3e]	12369	1			T2	11		T3	10		T11	8
valid_sources[0x3f]	12255	1			T1	1		T2	6		T3	19
valid_sources[0x40]	11899	1			T1	6		T2	16		T3	11
valid_sources[0x41]	13764	1			T1	9		T2	6		T3	5
valid_sources[0x42]	21386	1			T2	12		T3	11		T11	14
valid_sources[0x43]	16900	1			T1	7		T2	6		T3	11
valid_sources[0x44]	14363	1			T1	13		T2	13		T3	12
valid_sources[0x45]	13206	1			T2	14		T3	11		T7	6
valid_sources[0x46]	21968	1			T1	5		T2	5		T3	17
valid_sources[0x47]	13178	1			T1	10		T2	8		T3	12
valid_sources[0x48]	13443	1			T1	1		T2	19		T3	5
valid_sources[0x49]	14266	1			T1	6		T2	8		T3	8
valid_sources[0x4a]	12098	1			T2	6		T3	8		T7	1
valid_sources[0x4b]	14232	1			T1	12		T2	9		T3	9
valid_sources[0x4c]	12864	1			T1	9		T2	8		T3	13
valid_sources[0x4d]	12215	1			T1	2		T2	22		T3	9
valid_sources[0x4e]	12723	1			T2	14		T3	11		T7	2
valid_sources[0x4f]	12281	1			T1	1		T2	15		T3	13
valid_sources[0x50]	12396	1			T1	3		T2	9		T3	12
valid_sources[0x51]	12800	1			T1	5		T2	9		T3	14
valid_sources[0x52]	12341	1			T1	8		T2	15		T3	11
valid_sources[0x53]	19934	1			T2	7		T3	6		T11	5
valid_sources[0x54]	12853	1			T1	2		T2	14		T3	10
valid_sources[0x55]	12729	1			T1	7		T2	11		T3	17
valid_sources[0x56]	11727	1			T1	3		T2	5		T3	15
valid_sources[0x57]	12060	1			T1	2		T2	15		T3	17
valid_sources[0x58]	13594	1			T2	10		T3	11		T7	5
valid_sources[0x59]	13688	1			T1	6		T2	12		T3	11
valid_sources[0x5a]	26841	1			T1	3		T2	8		T3	6
valid_sources[0x5b]	37749	1			T1	14		T2	8		T3	8
valid_sources[0x5c]	12579	1			T1	2		T2	11		T3	8
valid_sources[0x5d]	15762	1			T1	8		T2	10		T3	16
valid_sources[0x5e]	14079	1			T1	2		T2	13		T3	15
valid_sources[0x5f]	13420	1			T1	10		T2	10		T3	9
valid_sources[0x60]	12815	1			T1	4		T2	12		T3	8
valid_sources[0x61]	18204	1			T1	9		T2	15		T3	10
valid_sources[0x62]	13335	1			T1	4		T2	14		T3	4
valid_sources[0x63]	13338	1			T2	14		T3	5		T11	21
valid_sources[0x64]	13253	1			T1	2		T2	8		T3	14
valid_sources[0x65]	12414	1			T2	13		T3	11		T7	3
valid_sources[0x66]	11614	1			T1	1		T2	11		T3	14
valid_sources[0x67]	16172	1			T1	7		T2	10		T3	17
valid_sources[0x68]	14671	1			T1	2		T2	21		T3	18
valid_sources[0x69]	21293	1			T1	10		T2	8		T3	10
valid_sources[0x6a]	12350	1			T1	7		T2	12		T3	14
valid_sources[0x6b]	13811	1			T1	2		T2	14		T3	7
valid_sources[0x6c]	12690	1			T2	5		T3	16		T7	1
valid_sources[0x6d]	14627	1			T2	10		T3	14		T7	4
valid_sources[0x6e]	14436	1			T1	1		T2	10		T3	13
valid_sources[0x6f]	12941	1			T1	7		T2	8		T3	12
valid_sources[0x70]	11746	1			T1	4		T2	11		T3	11
valid_sources[0x71]	14912	1			T1	5		T2	6		T3	15
valid_sources[0x72]	11633	1			T1	3		T2	10		T3	11
valid_sources[0x73]	14287	1			T1	4		T2	11		T3	17
valid_sources[0x74]	17557	1			T1	3		T2	13		T3	5
valid_sources[0x75]	13677	1			T1	14		T2	5		T3	14
valid_sources[0x76]	11927	1			T1	4		T2	4		T3	12
valid_sources[0x77]	12184	1			T1	4		T2	15		T3	20
valid_sources[0x78]	22995	1			T1	6		T2	5		T3	12
valid_sources[0x79]	12553	1			T1	6		T2	9		T3	7
valid_sources[0x7a]	13017	1			T1	9		T2	14		T3	11
valid_sources[0x7b]	11954	1			T1	1		T2	14		T3	2
valid_sources[0x7c]	12798	1			T2	10		T3	14		T7	1
valid_sources[0x7d]	12828	1			T1	13		T2	11		T3	5
valid_sources[0x7e]	13604	1			T1	9		T2	9		T3	5
valid_sources[0x7f]	18173	1			T2	10		T3	9		T11	9
valid_sources[0x80]	11769	1			T1	2		T2	10		T3	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

349115

1

T1

230

T2

173

T3

137

values[0x0]

all_enables

biggest_size

155183

1

T1

19

T2

41

T3

104

values[0x1]

all_enables

biggest_size

139684

1

T1

19

T2

17

T3

98