Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
22615059 |
22439629 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22615059 |
22439629 |
0 |
0 |
T1 |
12736 |
12608 |
0 |
0 |
T2 |
14543 |
14454 |
0 |
0 |
T3 |
25807 |
25756 |
0 |
0 |
T7 |
7627 |
7448 |
0 |
0 |
T11 |
11750 |
11674 |
0 |
0 |
T12 |
27759 |
27655 |
0 |
0 |
T13 |
32268 |
32184 |
0 |
0 |
T14 |
2847 |
2793 |
0 |
0 |
T15 |
85574 |
85459 |
0 |
0 |
T16 |
7724 |
7645 |
0 |
0 |